PIC16F883 Microchip Technology Inc., PIC16F883 Datasheet - Page 103

• Manufacturer Part Number: PIC16F883
• Description: 28/40/44-pin Flash-based, 8-bit Cmos Microcontrollers With Nanowatt Technology
• Manufacturer: Microchip Technology Inc.

TABLE 9-1:
FIGURE 9-2:
9.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 14.3 “Interrupts” for more
information.
© 2007 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
2:
3:
4:
F
F
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
/32
T
/2
/8
CY
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
to T
RC
ADC CLOCK PERIOD (T
AD
source has a typical T
Conversion Starts
ANALOG-TO-DIGITAL CONVERSION T
T
AD
1 T
ADCS<2:0>
AD
b9
AD
000
001
010
x11
2 T
)
AD
b8
3 T
AD
AD
b7
time of 4 μs for V
AD
PIC16F882/883/884/886/887
4 T
) V
2-6 μs
100 ns
400 ns
20 MHz
Preliminary
AD
1.6 μs
b6
S
5 T
. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
(1,4)
AD
(2)
(2)
AD
b5
time.
6 T
DD
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
AD
b4
> 3.0V.
7 T
2-6 μs
RC
250 ns
Device Frequency (F
1.0 μs
AD
8 MHz
4.0 μs
clock source is only recommended if the
AD
b3
CYCLES
(1,4)
8 T
(2)
(2)
AD
b2
9
T
AD
b1
2-6 μs
500 ns
8.0 μs
10 T
4 MHz
2.0 μs
OSC
AD
b0
(1,4)
(3)
(2)
11
)
DS41291D-page 101
2-6 μs
32.0 μs
8.0 μs
1 MHz
2.0 μs
(1,4)
(3)
(3)