EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 74

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

11.3
74
EV8AQ160
Clock Inputs (CLK/CLKN)
0846G–BDC–11/09
Figure 11-4. Differential Analog Input Implementation (DC Coupled)
Notes:
Differential mode is the recommended input scheme.Single-ended clock input is not recommended due
to performance limitations. Since the clock input common mode is 1.8V, we recommend to AC couple
the input clock as described in
Figure 11-5. Differential Clock Input Implementation (AC Coupled)
1. X = A, B, C or D.
2. The 50Ω terminations are implemented on-chip and can be fine tuned (TRIMMER register at address
3. CMIRefAB/CD = 1.8V. This Common mode is output on signal CMIRefAB for A and B channels and
V OCM (Source) =
50 Source
Differential
sinewave
Differential 50Ω
Ω
V ICM (ADC)
0x13).
CMIRefCD for C and D channels.
Source
10 nF
10 nF
Figure
11-5.
XAIN
XAI
V ICM
CLKN
CLK
50Ω
50Ω
(See Note 2
(See Note 2
(See Note 3
50
50
Ω
Ω
ADC Analog Input Buffer
V ICM
)
)
GND
)
= ~1.8V
ADC Clock Input Buffer
5.25 pF
V CC = 3.3V
GND
GND
20 pF
11.06 KΩ
12.68 K Ω
e2v semiconductors SAS 2009
CMIRefAB/CD