HT46RU66 Holtek Semiconductor Inc., HT46RU66 Datasheet
HT46RU66
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HT46RU66 Summary of contents
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... PFD function for sound generation Real Time Clock - RTC General Description The HT46RU66/HT46CU66 are 8-bit, high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for A/D product applications that interface directly to analog signals and which require an LCD Interface. The HT46CU66 mask version device, is fully pin and functionally compatible with its sister HT46RU66 OTP device ...
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... Block Diagram Rev. 1.20 HT46RU66/HT46CU66 2 October 2, 2007 ...
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... Pin Assignment Rev. 1.20 HT46RU66/HT46CU66 3 October 2, 2007 ...
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... Duty O COM3/SEG46 COM3 or SEG46 Rev. 1.20 HT46RU66/HT46CU66 Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software in- structions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors ...
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... DD4 (Crystal OSC, RC OSC) Operating Current I DD5 (f =32768Hz) SYS Rev. 1.20 HT46RU66/HT46CU66 Description Reference voltage input pin. Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground Positive analog power supply Negative analog power supply, ground +6.0V Storage Temperature ............................ 125 ...
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... I/O Port Segment Logic Output I OH1 Source Current LCD Common and Segment I OL2 Current LCD Common and Segment I OH2 Current Rev. 1.20 HT46RU66/HT46CU66 Test Conditions Min. V Conditions load, system HALT, LCD Off at HALT, UART Off load, system HALT, LCD On at HALT, C type, 5V UART Off ...
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... RES t System Start-up Timer Period SST t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note 1/f or 1/f SYS SYS1 SYS2 Rev. 1.20 HT46RU66/HT46CU66 Test Conditions V Conditions load =5V REF =5V, V =AV , ...
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... S13 S12 S11 S10 S9 Note: *13~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.20 HT46RU66/HT46CU66 Program Counter - PC The program counter is 14 bits wide and controls the se- quence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 16384 16 addresses. ...
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... Note: *13~*0: Table location bits @7~@0: Table pointer lower-order bits (TBLP) Rev. 1.20 HT46RU66/HT46CU66 Program Memory Location 004H Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, the interrupt is enabled, and the stack is not full, the pro- gram begins execution at location 004H. ...
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... Data Memory - RAM The Data Memory, RAM, has a structure of 620 8 bits, and is divided into two functional groups, namely; spe- cial function registers bits, and general purpose data memory (Bank 0: 192 8 bits, Bank 2: 192 8 bits Rev. 1.20 HT46RU66/HT46CU66 RAM Mapping 10 October 2, 2007 ...
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... MP0 and MP1 respectively. Reading loca- tion 00H or 02H indirectly returns the result 00H. Writing to it indirectly results to no operation. Rev. 1.20 HT46RU66/HT46CU66 The function of data movement between two indirect ad- dressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Data Memory in combination with their corre- sponding indirect addressing registers ...
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... External interrupts are triggered by an edge transition on pins INT0 or INT1 . A configuration option exists to Rev. 1.20 HT46RU66/HT46CU66 Function Status (0AH) Register select one of three transition types, either high to low, low to high or both. The related interrupt request flag, EIF0 ...
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... RTF Real time clock interrupt request flag (1=active; 0=inactive) Rev. 1.20 HT46RU66/HT46CU66 During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both the stack is not full ...
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... For applications where precise RTC frequencies are essential, these components may be re- quired to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 1.20 HT46RU66/HT46CU66 flag, RTF; bit 6 of the MFIC register, the time base inter- rupt flag, TBF; bit 5 of the MFIC register, indicate that a 04H related interrupt has occurred ...
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... If the WDT time-out is selected maximum time-out period is divided by 2 Rev. 1.20 HT46RU66/HT46CU66 give a time of about 2.1s~4.3s for the internal WDT os- cillator. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock. The WDT will operate in the same manner except that in the Power Down mode, the WDT will stop counting and lose its pro- tecting purpose ...
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... However wake-up results in the next instruction execution, the execution will be performed * immediately after the dummy period has finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the Power Down state. 16 HT46RU66/HT46CU66 (system SYS October 2, 2007 ...
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... SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the sys- tem awakens from the Power Down mode or during power up. Reset Timing Chart Rev. 1.20 HT46RU66/HT46CU66 The functional unit chip reset status is shown below. Program Counter 000H Interrupt Disabled ...
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... HT46RU66/HT46CU66 RES Reset WDT Time-out (HALT) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 00u0 00uu uuuu uuuu uuuu uuuu ...
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... T0ON/T1ON/ T2ON is auto- matically cleared after a measurement cycle is com T0ON/T1ON/T2ON can only be reset by instructions. 19 HT46RU66/HT46CU66 RES Reset WDT Time-out (HALT) (HALT)* 0000 00x0 ...
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... After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the Rev. 1.20 HT46RU66/HT46CU66 timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed af- ter the timer mode bits have been properly setup. Set- ...
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... Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 6 T0M0 10=Timer mode (internal clock) 7 T0M1 11=Pulse width measurement mode 00=Unused Rev. 1.20 Timer/Event Counter 2 PFD Source Option Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR0C (0EH) Register 21 HT46RU66/HT46CU66 October 2, 2007 ...
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... Defines the operating mode, T2M1, T2M0: 01=Event count mode (external clock) 6 T2M0 10=Timer mode (internal clock) 7 T2M1 11=Pulse width measurement mode 00=Unused Rev. 1.20 Function TMR1C (11H) Register Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR2C (2EH) Register 22 HT46RU66/HT46CU66 October 2, 2007 ...
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... PA3 Logical Input Note: The PFD frequencyisthetimer/eventcounter overflowfrequency dividedby2. Rev. 1.20 HT46RU66/HT46CU66 put/output latches can be set or cleared by the SET [m].i and CLR [m].i bit manipulation instructions. Some instructions first input data and then follow the out- put operations. For example, SET [m].i , CLR [m].i , CPL [m] , CPLA [m] read the entire port states into the CPU, execute the defined bit operations, and then write the results back to the latches or the accumulator ...
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... X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is the preload value for the timer/event counter f is input clock frequency for timer/event counter TMR Rev. 1.20 HT46RU66/HT46CU66 O/P (Normal) I/P (PWM) Logical Output Logical Input PA3 Data Register PA3 Pad State 0 ...
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... PWM1 and PWM2. Devices with four PWM outputs re- quire a further additional register known as PWM3 here that the 8-bit value, which represents the overall Rev. 1.20 HT46RU66/HT46CU66 PC6/TX Input/Output Ports PC7/RX Input/Output Ports duty cycle of one modulation cycle of the output wave- form, should be placed. To increase the PWM modula- ...
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... PWM operation impor- tant to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. 6+2 PWM Mode PWM Register for 6+2 Mode 26 HT46RU66/HT46CU66 PWM Register Name PWM0/PWM1/PWM2 PWM0/PWM1/PWM2/PWM3 AC (0~3) Duty Cycle i<AC ...
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... PWM output pins are setup as outputs. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing the Rev. 1.20 HT46RU66/HT46CU66 Parameter Modulation cycle i (i=0~1) 7+1 Mode Modulation Cycle Values The following diagram illustrates the waveforms asso- ciated with the 7+1 mode PWM operation ...
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... PB can be an analog input or setup as a normal I/O line, the selected function is determined by these 3 bits. Once a PB line is selected as an analog in- put, the I/O function and pull-high resistor of this I/O line Rev. 1.20 HT46RU66/HT46CU66 PD.0 will remain low PD.1 will remain low PD.2 will remain low PD.3 will remain low are disabled and the A/D converter circuit is pow- ered-on ...
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... AN4 AN3 PB6 AN5 AN4 AN3 AN6 AN5 AN4 AN3 Port B Configuration Bit5 Bit4 Bit3 ADRL (24H), ADRH (25H) Register 29 HT46RU66/HT46CU66 PB2 PB1 PB0 PB2 PB1 AN0 PB2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 ...
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... ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Rev. 1.20 HT46RU66/HT46CU66 /8 as the A/D clock SYS A/D Conversion Timing 30 October 2, 2007 ...
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... MAX else V connect to V MAX Rev. 1.20 HT46RU66/HT46CU66 only by indirect addressing mode using MP1. When data is written into the display data area automati- cally read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off written to the corresponding bit of the display memory, respectively ...
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... LCD Driver Output (1/3 Duty, 1/2 Byte, R/C Type) Rev. 1.20 HT46RU66/HT46CU66 32 October 2, 2007 ...
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... Rev. 1.20 HT46RU66/HT46CU66 LCD Driver Output 33 October 2, 2007 ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.20 HT46RU66/HT46CU66 Function RTCC (09H) Register The relationship between V Note: V ...
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... UART Bus Serial Interface The HT46RU66/HT46CU66 devices contain an inte- grated full-duplex asynchronous serial communications UART interface that enables communication with exter- nal devices that contain a serial interface. The UART function has many features and can transmit and re- ceive data serially by transferring a frame of data with ...
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... NF, FERR, and/or PERR are set within the same clock cycle. The Rev. 1.20 HT46RU66/HT46CU66 RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR reg- ister, and if the RXR register has no data available. ...
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... STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are Rev. 1.20 HT46RU66/HT46CU66 used, if the bit is equal to 0 then only one stop bit is used. PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected ...
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... If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal Rev. 1.20 HT46RU66/HT46CU66 to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. ...
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... Baud Rates for BRGH=0 f =7.159MHz f =4MHz SYS SYS Error Kbaud BRG Kbaud 207 0.300 1.203 0.23 51 1.202 2.38 -0.83 25 2.404 4.863 1.32 12 4.808 9.322 -2.9 6 8.929 18.64 -2.9 2 20.83 37.29 -2.9 1 55.93 -2.9 0 62.5 111.86 -2.9 39 HT46RU66/HT46CU66 f SYS 1 (BRx64) 8000000 1 12.0208 x ( 9600 64 ) 9615 = 0.16% f =3.579545MHz SYS Error Error BRG Kbaud 0.00 185 0.300 0.00 0.16 46 1.19 -0.83 0.16 22 2.432 1.32 0.16 11 4.661 -2.9 -6.99 5 9.321 -2.9 8. ...
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... The fol- lowing table shows various formats for data trans- mission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. 40 HT46RU66/HT46CU66 f =3.579545MHz SYS Error BRG Kbaud Error 0 ...
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... The TX output pin will then return to having a normal general purpose I/O pin function. Rev. 1.20 HT46RU66/HT46CU66 Transmitting data Stop When the UART is transmitting data, the data is Bit shifted on the TX pin from the shift register, with the least significant bit first ...
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... Setup the BRG register to select the desired baud rate. Rev. 1.20 HT46RU66/HT46CU66 Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. At this point the receiver will be enabled which will begin to look for a start bit ...
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... RXIF bit. Data will be transferred from the Shift register to the RXR register. Rev. 1.20 HT46RU66/HT46CU66 No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation ...
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... This option is to determine crystal or 32768Hz crystal oscillator is chosen as system clock. WDT, RTC and time base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. Rev. 1.20 HT46RU66/HT46CU66 mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par- ity enable bit to zero. ...
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... PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low. Rev. 1.20 HT46RU66/HT46CU66 Options ...
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... RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to Application Note HA0075E for more information. Rev. 1.20 HT46RU66/HT46CU66 46 October 2, 2007 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.20 HT46RU66/HT46CU66 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.20 HT46RU66/HT46CU66 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 HT46RU66/HT46CU66 Description 49 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.20 HT46RU66/HT46CU66 50 October 2, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.20 HT46RU66/HT46CU66 addr 51 October 2, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT46RU66/HT46CU66 October 2, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.20 HT46RU66/HT46CU66 addr 53 October 2, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.20 Stack Stack Stack [m]. 0~6) 54 HT46RU66/HT46CU66 October 2, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.20 [m]. 0~6) 55 HT46RU66/HT46CU66 October 2, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.20 [ HT46RU66/HT46CU66 October 2, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.20 0 [m] [ HT46RU66/HT46CU66 October 2, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.20 HT46RU66/HT46CU66 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 58 October 2, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.20 HT46RU66/HT46CU66 59 October 2, 2007 ...
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... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Rev. 1.20 HT46RU66/HT46CU66 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 October 2, 2007 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 1.20 HT46RU66/HT46CU66 Dimensions in mil Min. Nom. 395 291 8 720 Max. 420 299 12 730 October 2, 2007 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 1.20 Dimensions in mm Min. Nom. 18.50 13.90 24.50 19.90 0.65 0.30 2.50 0. HT46RU66/HT46CU66 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20 7 October 2, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT46RU66/HT46CU66 63 October 2, 2007 ...