HT46RU66 Holtek Semiconductor Inc., HT46RU66 Datasheet - Page 36

• Manufacturer Part Number: HT46RU66
• Description: Ht46ru66/ht46cu66 -- A/d Type 8-bit Mcu With Lcd
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.20
USR register
The USR register is the status register for the UART,
which can be read by the program to determine the
present status of the UART. All flags within the USR
register are read only.
Further explanation on each of the flags is given below:
TXIF
The TXIF flag is the transmit data register empty
flag. When this read only flag is 0 it indicates that
the character is not transferred to the transmit shift
registers. When the flag is 1 it indicates that the
transmit shift register has received a character from
the TXR data register. The TXIF flag is cleared by
reading the UART status register (USR) with TXIF
set and then writing to the TXR data register. Note
that when the TXEN bit is set, the TXIF flag bit will
also be set since the transmit buffer is not yet full.
TIDLE
The TIDLE flag is known as the transmission com-
plete flag. When this read only flag is 0 it indicates
that a transmission is in progress. This flag will be
set to 1 when the TXIF flag is 1 and when there
is no transmit data, or break character being trans-
mitted. When TIDLE is 1 the TX pin becomes idle.
The TIDLE flag is cleared by reading the USR regis-
ter with TIDLE set and then writing to the TXR regis-
ter. The flag is not generated when a data character,
or a break is queued and ready to be sent.
RXIF
The RXIF flag is the receive register status flag.
When this read only flag is 0 it indicates that the
RXR read data register is empty. When the flag is
tains new data. When the contents of the shift regis-
ter are transferred to the RXR register, an interrupt
is generated if RIE=1 in the UCR2 register. If one or
more errors are detected in the received word, the
appropriate receive-related flags NF, FERR, and/or
PERR are set within the same clock cycle. The
1 it indicates that the RXR read data register con-
36
RXIF flag is cleared when the USR register is read
with RXIF set, followed by a read from the RXR reg-
ister, and if the RXR register has no data available.
RIDLE
The RIDLE flag is the receiver status flag. When this
read only flag is 0 it indicates that the receiver is
between the initial detection of the start bit and the
completion of the stop bit. When the flag is 1 it in-
dicates that the receiver is idle. Between the com-
pletion of the stop bit and the detection of the next
start bit, the RIDLE bit is 1 indicating that the
UART is idle.
OERR
The OERR flag is the overrun error flag, which indi-
cates when the receiver buffer has overflowed.
When this read only flag is 0 there is no overrun er-
ror. When the flag is 1 an overrun error occurs
which will inhibit further transfers to the RXR receive
data register. The flag is cleared by a software se-
quence, which is a read to the status register USR
followed by an access to the RXR data register.
FERR
The FERR flag is the framing error flag. When this
read only flag is 0 it indicates no framing error.
When the flag is 1 it indicates that a framing error
has been detected for the current character. The
flag can also be cleared by a software sequence
which will involve a read to the USR status register
followed by an access to the RXR data register.
NF
The NF flag is the noise flag. When this read only
flag is 0
the flag is 1 it indicates that the UART has de-
tected noise on the receiver input. The NF flag is set
during the same cycle as the RXIF flag but will not
be set in the case of an overrun. The NF flag can be
cleared by a software sequence which will involve a
read to the USR status register, followed by an ac-
cess to the RXR data register.
it indicates a no noise condition. When
HT46RU66/HT46CU66
October 2, 2007