HT46RU25 Holtek Semiconductor Inc., HT46RU25 Datasheet - Page 23

• Manufacturer Part Number: HT46RU25
• Description: Ht46ru25/ht46cu25 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The I/O functions of PA3 are shown below.
Note:
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Note:
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). The I/O func-
tions of PD0/PD1/PD2/PD3 are as shown.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 4 channels (6+2)/(7+1)
(depending on options) bits PWM output shared with
PD0/PD1/PD2/PD3. The PWM channels have their data
registers denoted as PWM0 (1AH), PWM1 (1BH),
PWM2 (1CH) and PWM3 (1DH). The frequency source
Rev. 1.30
Mode
Timer
PA3
I/O
Mode
Off
Off
On
On
PD0
PD1
PD2
PD3
I/O
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
(Normal)
timer/event counter
X stands for unused
U stands for unknown
M is 65536 for Timer0, Timer1 PFD,
256 for Timer2 PFD
N is preload value for timer/event counter
f
Preload
TMR
Logical
Timer
Value
Input
I/P
(Normal)
X
X
N
N
Logical
Input
is the input clock frequency for the
I/P
Register
(Normal)
Data
Logical
PA3
Output
(Normal)
0
1
0
1
O/P
Logical
Output
O/P
State
PFD
PA3
Pad
Logical
U
0
0
(PFD)
Input
Logical
(PWM)
I/P
Input
I/P
f
TMR
Frequency
(Timer on)
/[2 (m n)]
PFD
(PFD)
(PWM)
PWM0
PWM1
PWM2
PWM3
X
X
X
PFD
O/P
O/P
23
of the PWM counter comes from f
ters are four 8-bit registers. The waveforms of the PWM
outputs are as shown. Once the PD0/PD1/PD2/PD3 are
selected as the PWM outputs and the output function of
the PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/
PDC.2/PDC.3 = 0 ), writing 1 to PD0/PD1/PD2/PD3
data register will enable the PWM output function and
writing 0 will force the PD0/PD1/PD2/PD3 to remain
at 0 .
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
f
f
SYS
SYS
Modulation cycle i
Modulation cycle i
Modulation Frequency
/64 for (6+2) bits mode
/128 for (7+1) bits mode
Parameter
Parameter
(i=0~1)
(i=0~3)
PWM
HT46RU25/HT46CU25
AC (0~1)
AC (0~3)
i<AC
i<AC
i AC
i AC
PWM Cycle
Frequency
f
SYS
SYS
/256
. The PWM regis-
Duty Cycle
March 9, 2007
Duty Cycle
PWM Cycle
[PWM]/256
DC+1
DC+1
128
128
DC
DC
64
64
Duty