HT46RU25 Holtek Semiconductor Inc., HT46RU25 Datasheet - Page 28

• Manufacturer Part Number: HT46RU25
• Description: Ht46ru25/ht46cu25 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

I
I
bidirectional two-wire lines. The data line and clock line
are implement in SDA pin and SCL pin. The SDA and
SCL are NMOS open drain output pin. They must con-
nect a pull-high resistor respectively.
Using the I
data. One is in slave transmit mode, the other is in slave
receive mode. There are four registers related to I
Bus; HADR([20H]), HCR([21H]), HSR([22H]),
HDR([23H]). The HADR register is the slave address
setting of the device, if the master sends the calling ad-
dress which match, it means that this device is selected.
The HCR is I
device enable or disable the I
as a receiver. The HSR is I
sponds with the I
data register, data to transmit or receive must be via the
HDR register.
The I
HEN bit defines whether to enable or disable the I
Bus. If the data wants to transfer via I
must be set. The HTX bit defines whether the I
in transmit or receive mode. If the device is as a trans-
mitter, this bit must be set to 1 . The TXAK defines the
transmit acknowledge signal, when the device received
8-bit data, the device sends this bit to I
clock. If the receiver wants to continue to receive the
next data, this bit must be reset to 0 before receiving
data.
The I
is reset to 0 when one data byte is being transferred. If
one data transfer is completed, this bit is set to 1 . The
HAAS bit is set to 1 when the address is matched, and
the I
rupt is enabled and the stack is not full, a subroutine call
to location 10H will occur. Writing data to the I
control register clears HAAS bit. If the address is not
matched, this bit is reset to 0 . The HBB bit is set to re-
spond when the I
signal is detected. This bit is reset to 0 when the I
Bus is not busy. It means that a STOP signal is detected
and the I
read/write command bit, if the calling address is
matched. When HAAS is set to 1 , the device checks
the SRW bit to determine whether the device is working
in transmit or receive mode. When the SRW bit is set to
I
Rev. 1.30
2
2
2
1 , it means that the master wants to read data from the
C Bus Serial Interface
C Bus is implemented in the device. The I
C Bus, the slave device must write data to the I
2
2
C Bus interrupt request flag is set to 1 . If the inter-
2
C Bus status register contains 5 bits. The HCF bit
C Bus control register contains three bits. The
2
2
C Bus is free. The SRW bit defines the
C Bus, the device has two ways to transfer
2
C Bus control register which defines the
2
2
C Bus status. The HDR is input/output
C Bus is busy. It means that a START
2
C Bus status register, it re-
2
C Bus as a transmitter or
2
C Bus at the 9th
2
C Bus, this bit
2
C Bus is a
2
C Bus is
2
2
C Bus,
C Bus
2
2
2
C
C
C
28
so the slave device is working in transmit mode. When
SRW is reset to 0 , it means that the master wants to
write data to the I
data from the bus, so the slave device is working in re-
ceive mode. The RXAK bit is reset to 0 indicates that
an acknowledge signal has been received. In the trans-
mit mode, the transmitter checks the RXAK bit to deter-
mine the receiver which wants to receive the next data
byte, so the transmitter continues to write data to the I
Bus until the RXAK bit is set to 1 and the transmitter
releases the SDA line, so that the master can send the
STOP signal to release the bus.
The HADR bit7-bit1 define the device slave address. At
the beginning of a transfer, the master must select a de-
vice by sending the address of the slave device. The bit
0 is unused and is not defined. If the I
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is matched, the HAAS sta-
tus bit is set and generates an I
ISR, the slave device must check the HAAS bit to deter-
mine whether the I
slave address that has matched or completed one 8-bit
data transfer. The last bit of the 8-bit data is read/write
command bit, it responds in SRW bit. The slave will
check the SRW bit to determine whether the master
wants to transmit or receive data. The device checks the
SRW bit to know if it s a transmitter or a receiver.
The HDR register is the I
ter. Before transmitting data, the HDR must write the
data which needs to be transmitted. Before receiving
data, the device must dummy read data from the HDR.
Transmitting or Receiving data from the I
via the HDR register.
At the beginning of the transfer of the I
vice must initialize the bus, the following are the notes
for initializing the I
Note:
means undefined
Slave Address
1: Write the I
define its own slave address.
2: Set HEN bit of the I
(HCR) bit 0 to enable the I
3: Set EHI bit of the interrupt control register 1
(INTC1) bit 0 to enable the I
Bit7~Bit1
HADR (20H) Register
2
2
C Bus:
C Bus, the slave device must read
HT46RU25/HT46CU25
2
2
C Bus interrupt comes from the
C Bus address register (HADR) to
2
C Bus input/output data regis-
2
2
C Bus control register
C Bus interrupt. In the
2
C Bus.
2
2
C Bus interrupt.
C Bus receives a
Bit0
2
2
C Bus, the de-
C Bus must be
March 9, 2007
2
C