DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 141

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

13.0
13.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required. These steps assume timer source is
initially turned off but this is not a requirement for the
module operation.
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output
3. Calculate the time to the falling edge of the pulse
4. Write the value computed in step 2 into the Output
5. Set Timer Period register, PRy, to a value equal to
6. Set the OCM bits to ‘100’ and the OCTSEL
7. Set the TON (TyCON<15>) bit to ‘1’, which
8. To initiate another single pulse output, change the
© 2007 Microchip Technology Inc.
Note:
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
pulse relative to the TMRy start value (0000h).
based on the desired pulse width and the time to
the rising edge of the pulse.
Compare register, OCxR, and the value computed
in step 3 into the Output Compare Secondary
register, OCxRS.
or greater than value in OCxRS, the Output
Compare Secondary register.
(OCxCON<3>) bit to the desired timer source. The
OCx pin state will now be driven low.
enables the compare time base to count. Upon the
first match between TMRy and OCxR, the OCx pin
will be driven high.
When the incrementing timer, TMRy, matches the
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses
are driven onto the OCx pin and it remains at low.
As a result of the second compare match event,
the OCxIF interrupt flag bit is set. This will result in
an interrupt if it is enabled by setting the OCxIE bit.
For further information on peripheral interrupts,
refer to Section 6.0 “Interrupt Controller”.
Timer and Compare register settings, if needed,
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com)
dsPIC33F
chapters.
Family
Reference
for
the
Manual
latest
Preliminary
dsPIC33FJ12MC201/202
The output compare module does not have to be
disabled after the falling edge of the output pulse.
Another pulse can be initiated by rewriting the value of
the OCxCON register.
13.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
To configure the module for generation of a continuous
stream of output pulses, the following steps are
required. These steps assume timer source is initially
turned off, but this is not a requirement for the module
operation.
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output pulse
3. Calculate the time to the falling edge of the pulse,
4. Write the values computed in step 2 into the Output
5. Set Timer Period register, PRy, to a value equal to
6. Set the OCM bits to ‘101’ and the OCTSEL bit to the
7. Enable the compare time base by setting the TON
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling the timer, and clearing
the TMRy register, are not required, but may be
advantageous for defining a pulse from a known
event time boundary.
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
relative to the TMRy start value (0000h).
based on the desired pulse width and the time to the
rising edge of the pulse.
Compare register, OCxR, and value computed in
step 3 into the Output Compare Secondary register,
OCxRS.
or greater than value in OCxRS, the Output
Compare Secondary register.
desired timer source. The OCx pin state will now be
driven low.
(TyCON<15>) bit to ‘1’. Upon the first match
between TMRy and OCxR, the OCx pin will be
driven high.
When the compare time base, TMRy, matches the
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin.
As a result of the second compare match event,
the OCxIF interrupt flag bit is set. When the com-
pare time base and the value in its respective
Timer Period register match, the TMRy register
resets to 0x0000 and resumes counting.
These events repeat and a continuous stream of
pulses is generated indefinitely. The OCxIF flag is
set on each OCxRS-TMRy compare match event.
Setup for Continuous Output
Pulse Generation
DS70265B-page 139