DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet - Page 16

• Manufacturer Part Number: DSPIC33FJ12MC202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ12MC201/202
2.4
REGISTER 2-1:
DS70265B-page 14
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
R/W-0
R-0
OA
2:
3:
CPU Control Registers
(2)
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
IPL<2:0>
R/W-0
Note:
of the result occurred
data) of the result occurred
R-0
OB
SR: CPU STATUS REGISTER
(3)
(2)
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
R/W-0
R/C-0
SA
(1)
(3)
R/C-0
SB
R-0
RA
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
R/W-0
OAB
R-0
(1)
(1)
N
R/W-0
R/C-0
SAB
OV
© 2007 Microchip Technology Inc.
R/W-0
R -0
DA
Z
R/W-0
R/W-0
DC
C
bit 8
bit 0