DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 59

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DSPIC30F4013

Manufacturer Part Number
DSPIC30F4013
Description
Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet

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TABLE 8-2:
© 2007 Microchip Technology Inc.
Highest Natural Order Priority
Lowest Natural Order Priority
Number
28-40
43-53
INT
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
41
42
11
0
1
2
3
4
5
6
7
8
9
Number
Vector
36-48
51-61
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
49
50
11
8
9
dsPIC30F4013 INTERRUPT
VECTOR TABLE
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer 1
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 V Timer 2
T3 – Timer 3
SPI1
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
SI2C – I
MI2C – I
Input Change Interrupt
INT1 – External Interrupt 1
IC7 – Input Capture 7
IC8 – Input Capture 8
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer 4
T5 – Timer 5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
Reserved
C1 – Combined IRQ for CAN1
Reserved
DCI – CODEC Transfer Done
LVD – Low-Voltage Detect
Reserved
2
Interrupt Source
2
C™ Slave Interrupt
C Master Interrupt
8.2
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
8.2.1
In addition to external Reset and Power-on Reset
(POR), these sources of error conditions ‘trap’ to the
Reset vector:
• Watchdog Time-out:
• Uninitialized W Register Trap:
• Illegal Instruction Trap:
• Brown-out Reset (BOR):
• Trap Lockout:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
An attempt to use an uninitialized W register as
an Address Pointer causes a Reset.
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Occurrence of multiple trap conditions
simultaneously causes a Reset.
dsPIC30F3014/4013
Reset Sequence
RESET SOURCES
DS70138E-page 57

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