NSD-2101 austriamicrosystems, NSD-2101 Datasheet - Page 10

• Manufacturer Part Number: NSD-2101
• Description: Piezo Motor Driver Asic For Sql-rv Series Reduced Voltage Squiggle Rv And Utaf? Motors
• Manufacturer: austriamicrosystems

NSD-2101
Preliminary Data Sheet - D e t a i l e d D e s c r i p t i o n
7.5 Register Map
Table 8
Table 8. I²C Registers
7.6 Control Register
The control register is used to trigger frequency calibration as well as to select and enable the drive phases.
Table 9. Control Register
www.austriamicrosystems.com/NSD-2101
Pulse count (high byte)
Pulse count (low byte)
Reserved register
Control Register
Hybrid speed
Description
Period count
Period offset
Pulse width
Phase shift
Control Flag Mask
lists out the registers which can be addressed over the I²C interface.
1000 0000
0100 0000
0010 0000
0001 0000
Address
00h
01h
02h
03h
04h
05h
06h
07h
10h
MSB
IDL
X
P
X
X
X
X
X
PS[1] PS[0]
HB
X
D
X
X
X
X
X
Abbr
PS[1]
PS[0]
DS[1] DS[0]
HYB
X
X
X
X
X
X
DT
Data Byte
X
X
X
X
X
X
Revision 0.2
CN[1] CN[0]
X
X
X
X
X
X
Default
0
1
1
0
X
X
X
X
X
X
X
X
P1
X
X
X
X
X
X
X
X
LSB
Reserved (leave 0)
Phase Select for sensing: PS[1] PS[0]:
00=None
01=Phase1
10=Phase2
11= Both Phases
Reserved (leave 0)
P2
X
X
X
X
X
X
X
X
P: Period count MSB;
D: Direction bit;
DS: Dead time selection bits: ‘00’=2,
‘01’=4, ‘10’=6 and ‘11’=8 VCO clocks.
CN needs to be 00 to enable Period
offset. Period offset is not used when
either Incremental or Sweep Frequency
Tracking is active.
IDL: Sets idle mode;
HB: Enable half bridge operation if VDD
> HB
HYB: Enable hybrid speed control;
DT: Enable signal for increased dead
time;
Selection bits(DS[1:0]) are only valid
when DT=1;
Selection bits should not be changed
when the output driver is active.
Hybrid Speed register: 0… half bridge;
128…full bridge operation; linear
transition for values in between;
Default: 128. Values from 1 to 127 are
used for linear speed control.
Reserved register used for device test
only, not accessible during normal
operation.
th
;
Description
Note
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