NSD-2101 austriamicrosystems, NSD-2101 Datasheet - Page 12

• Manufacturer Part Number: NSD-2101
• Description: Piezo Motor Driver Asic For Sql-rv Series Reduced Voltage Squiggle Rv And Utaf? Motors
• Manufacturer: austriamicrosystems

NSD-2101
Preliminary Data Sheet - D e t a i l e d D e s c r i p t i o n
7.9 Pulse Width Control
A register is used to define the duty cycle of the driver output signal. The default value for this register set during power up or power down (XPD
= LOW) is equal to 00h. In this case the default duty cycle of 50% is generated. The resulting duty cycle and resolution of single steps is
depending on the master clock frequency and the switching frequency of the driver output.
clock and 200kHz driver frequency. The value of the duty cycle register should not exceed 50.4% of the period counter value. Pulse Width
Modulation is used for speed control when motor is operating in half bridge mode.
Table 12. Pulse Width Register Values
If operating in half bridge mode, the pulse width can be used to adjust speed. At 50% the motor will operate at its maximum speed. To reduce the
speed, the pulse width may be reduced. However, below ~15%, there may not be enough energy in the signal to move the motor.
7.10 Phase Shift
A register is used to define the phase shift between the two phases of the driver output signal. The default value for this register set during power
up or power down (XPD = LOW) is equal to 00h. In this case the default phase shift of 90° is generated. The resulting phase shift and resolution
of single steps is depending on the master clock frequency and the switching frequency of the driver output.
25MHz master clock and 200kHz driver frequency. The value of the phase shift register should not exceed 50.4% of the period counter value.
Negative phase shift values are achieved by changing the direction bit: -160deg = 20deg and inverted direction bit.
Table 13. Phase Shift Register Values
7.11 Period Offset
Period Offset register defines the offset which is added to the period counter to shift the switching frequency. It also provides some additional
control bits.
This offset is only activated when frequency tracking is stopped. An offset has been provided as some types of motors operate better at slightly
below mechanical resonance.
supposed to lower drive frequency.
Table 14. Period Offset Register Values
www.austriamicrosystems.com/NSD-2101
Period Offset Register
Pulse Width Register
Phase Shift Register
0000 0000
0000 0001
0000 0000
0000 0001
0010 0000
0000 0000
0000 0001
0000 0010
0000 1101
0001 1011
0011 0101
0000 1101
0000 1110
0011 1110
0011 1111
0001 1111
Table 14
provides an example for 25MHz master clock and 200kHz nominal driver frequency. Period offset is only
49.6/50.4
37.44
40.32
89.28
92.16
10.4
21.6
42.4
49.6
50.4
90.5
2.88
-0.8
-1.6
Typ
Typ
Typ
0.8
0
Revision 0.2
Unit
Unit
Unit
deg
deg
deg
deg
deg
deg
%
%
%
%
%
%
%
%
%
%
Table 12
Default (Normal for both SQL and UTAF)
Default, no change of drive frequency
provides an example for 25MHz master
Table 13
Conditions
Conditions
Conditions
default
provides an example for
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