EM65565A ELAN Microelectronics Corp, EM65565A Datasheet - Page 19

• Manufacturer Part Number: EM65565A
• Description: 65 Com/ 132 Seg Stn Lcd Driver
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
6.1.2 Chip Select
The EM65565A IC has two chip select terminals: /CS1 and CS2. The MPU interface or
the serial interface is enabled only when /CS1=”L” and CS2=”H”. When chip select is
inactive, D0 to D7 enter a high impedance state and the D/I, /RD, and /WR inputs are
inactive. When serial interface is selected, the shift register and the counter are reset.
6.1.3 Accessing the DDRAM and the Internal Registers
To match the operation frequencies between the MPU and DDRAM or internal register,
the EM65565A performs a sort of LSI-LSI pipelining via the bus holder attached to the
internal data bus.
When the MPU writes data to the DDRAM, once the data is stored in the bus holder, it
is written to the DDRAM before the next data write cycle. Moreover, when the MPU
reads the DDRAM, the first data read cycle (dummy) stores the read data in the bus
holder, and then the data is read from the bus holder to the system bus at the next data
read cycle.
There is a certain restriction in the read sequence of the DDRAM. It should be noted
that data of the specified address is not generated by the read instruction issued
immediately after the address setup. This data is generated during the second time
data read. Thus, a dummy read is required whenever an address setup or write cycle
operation is conducted. This relationship is shown in Figure 3.
6.1.4 Busy Flag
The busy flag is output to pin D7 by a read status command. When the busy flag is “1”
it indicates that the EM65565A IC is executing its internal operations, and any
command other than status read is rejected during this time. If the cycle time (t
maintained, this flag need not be checked before each command. This makes it
possible for vast improvements in MPU processing capabilities.
1.
2.
3.
When the IC is not active, the shift registers and counter are reset to their initial
states.
Reading is not possible while in serial interface mode.
Caution is required on the SCL signal when it comes to line-end reflections and
external noise. It is recommended that operation be rechecked on the actual
equipment.
NOTE
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EM65565A
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