STSMIA832 STMicroelectronics, STSMIA832 Datasheet - Page 11

• Manufacturer Part Number: STSMIA832
• Description: 1.8v/2.8v High Speed Dual Differential Line Receivers, Standard Mobile Imaging Architecture Smia Decoder Deserializer
• Manufacturer: STMicroelectronics

STSMIA832
Figure 9.
3.7
3.8
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STSMIA832 Load capacitance and rise and fall time of LVTTL parallel outputs
Board layout
To obtain the maximum benefit from the noise and EMI reductions of subLVDS, attention
should be paid to the layout of differential lines. Lines of a differential pair should always be
adjacent to eliminate noise interference from other signals and take full advantage of the
noise canceling of the differential signals. Equal length should be maintained on signal
traces for a given differential pair. As with any high-speed design, the impedance
discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on
traces). Any discontinuities which do occur on one signal line should be mirrored in the other
line of the differential pair. Care should be taken to ensure that the differential trace
impedance match the differential impedance of the selected physical media (this impedance
should also match the value of the termination resistor (100 ohms) that is connected across
the differential pair at the receiver’s input). Surface mount resistors are recommended to
avoid the additional inductance that accompanies leaded resistors.
These resistors should be placed as close as possible to the receiver input pins to reduce
stubs and effectively terminate the differential lines. All of these considerations will limit
reflections and crosstalk which adversely effect high frequency performance and EMI.
Decoupling capacitors
Bypassing capacitors are needed to reduce the impact of switching noise which could limit
performance. For a conservative approach three parallel-connected decoupling capacitors
(Multi-Layered Ceramic capacitors in surface mount form factor) between each V
ground plane(s) are recommended. An example is shown in the figure below. Wide traces
for power and ground should be used and it should be ensured each capacitor has its own
via to the ground plane.
Application information
CC
and the
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