STW4811M STMicroelectronics, STW4811M Datasheet - Page 41

• Manufacturer Part Number: STW4811M
• Description: Power Management For Multimedia Processors
• Manufacturer: STMicroelectronics

STw4811M/STw4811N
4.3.2
Note:
Note:
4.3.3
VCORE regulator: DC/DC STEP- DOWN regulator
This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down
regulator that generates the regulated power supply with very high efficiency. The 16 voltage
levels enable dynamic voltage and frequency scaling suitable for any supply voltage of
CMOS process, they also follow the processor process roadmap. The regulated output
voltage level is adjustable via the main I2C interface (SDA, SCL): in high power mode by the
power control registers (
The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to
generate the switching clock of the SMPS. When this clock is not available, regulators run
with the internal RC oscillator.
The DC/DC step-down regulator has the following main features;
●
By default ‘vcore_sel’ = ‘vcore_sleep’
●
The definition of sleep mode is given in section
●
VIO_VMEM regulator: DC/DC step- down regulator
VIO_VMEM step-down regulator has the same structure than VCORE.
The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals.
This regulator can be used to supply the memories working with the multimedia processor,
such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to
generate the 1.8 V regulated power supply with very high efficiency.
The master clock (13, 19.2 or 26 MHz) is automatically detected and divided to generate the
SMPS switching clock. Master clock is squared when bit en_clock_squarer is enabled
(
regulators can run with the internal RC oscillator.
Table 25: Power control register at address 08h
Programmable output voltage,
–
–
–
3 power domains:
–
–
–
Soft start circuitry at start up, from power off to high power mode, when PON ball
changes from “0” to “1”.
When changing the output voltage value (during a voltage scaling phase) the
voltage step must be less than 100mV.
In high power mode, 16 levels from 1.0 V to 1.45 V through ‘vcore_sel [3:0]’ bits of
power control register (
In sleep mode,16 levels from 1.0 V to 1.45 V through ‘vcore_sleep [3:0]’ bits of
Vcore_sleep register (
‘High power mode’ when multimedia processor is in run mode, 600 mA full load
‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current
capability.
Fast switching from low current to high power mode.
The regulator is in ‘low current mode’ when multimedia processor is in sleep
mode. PWREN signal indicates that the multimedia processor is about to switch to
high power mode. VDDOK signal indicates to the multimedia processor that all
supplies are in the specified range.
‘Power down mode’ or ‘standby mode’ when regulator is switched off, no
consumption (‘en_vcore’ bit of power contro l register -
Table 22
Table 29
), in sleep mode by Vcore_sleep register (
Table 22
).
)
4.2.3: Sleep
). When this clock is not available,
mode.
Table 24
Functional description
)
Table 29
).
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