BU8255KVT ROHM Co. Ltd., BU8255KVT Datasheet

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BU8255KVT

Manufacturer Part Number
BU8255KVT
Description
35bit Lvds Receiver 5 35 Deserializer
Manufacturer
ROHM Co. Ltd.
Datasheet

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LVDS Interface ICs
35bit LVDS Receiver
5:35 DeSerializer
BU8255KVT
●Description
●Features
●Applications
Status of this document
◇Precaution
The Japanese version of this document is the formal specification.
A customer may use this translation version only for a reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and
number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number
by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
Flat Panel Display
・This chip is not designed to protect from radioactivity.
・The chip is made strictly for the specific application or equipment.
・This document may be used as strategic technical data which subjects to COCOM regulations.
■Five channels of LVDS data stream are converted to 35bits data of parallel LVCMOS level outputs.
■30bits of RGB output data, 5bits of timing and control output data(HSYNC, VSYNC, DE, CTL1 and CTL2)
■Support clock frequency from 8MHz up to 112MHz.
■Support consumer video format including 480i, 480P, 720P and 1080i as well.
■Support many kinds of PC video formats such as VGA, SVGA, XGA and SXGA.
■Provide 784Mbps per 1ch or 3.92Gbps per device throughput rate using 112MHz clock rate.
■User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock.
■30bit LVDS transmitter is recommended to use BU8254KVT.
Then it is necessary that the unit is measured as need.
are transmitted available.
Jun.2008

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BU8255KVT Summary of contents

Page 1

... LVDS Interface ICs 35bit LVDS Receiver 5:35 DeSerializer BU8255KVT ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ...

Page 2

Diagram LVDS Differential Input RCLK +/- (8~112MHz) RA +/- RB +/- RC +/- RD +/- RE +/- LVCMOS Input RESERVE PD OE R/F + PLL - 7 Sampling Clocks + Serial to Parallel - + Serial to Parallel - ...

Page 3

... Package Specification 1PIN MARK BU8255KVT Lot No. Figure–2 TQFP64V Package Product No. ...

Page 4

Diagram RA_ 49 50 RA+ RB_ 51 52 RB+ 53 LVDD 54 RC_ 55 RC+ 56 RCLK_ RCLK+ 57 LGND 58 RD_ 59 60 RD+ 61 RE_ 62 RE+ 63 PGND PVDD 64 64-Pin TQFP (Top View) Figure-3 Pin ...

Page 5

Description Table .1: Pin description Pin Name Pin No. RA+, RA- 50,49 RB+, RB- 52,51 RC+, RC- 55,54 RD+, RD- 60,59 RE+, RE- 62,61 RCLK+, 57,56 RCLK- 40,41,42,43, RA6~RA0 45,46,47 32,33,34,35, RB6~RB0 36,38,39 22,24,25,26, RC6~RC0 27,28,29 14,15,17,18, RD6~RD0 19,20,21 ...

Page 6

Description Table .2: Function explanation list PD R *1:Rxn x = A,B,C,D ...

Page 7

Characteristics ■Rating Table .3: Absolute maximum rating Item Supply voltage Input voltage Output voltage Storage temperature range Table .4: Package power Package TQFP64V *1 At temperature Ta > 25℃ *2 Package power when mounting on the PCB board. The ...

Page 8

Characteristics Table .6: LVCMOS DC character (V Symbol Item V High Input voltage IH V Low Input voltage IL V High Output voltage OH V Low Output voltage OL I Input current INC Table .7: LVDS Receiver DC character ...

Page 9

Current Table .8: Supply current Symbol Item Receiver supply current I RCCG (Gray Scale Pattern) Receiver supply current I RCCW (Worst Case Pattern) Receiver power down I RCCS supply current Gray Scale Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 ...

Page 10

Characteristics Table .9 : Switching characteristics Symbol t CLKOUT period RCP t CLKOUT "H" time RCH t CLKOUT "L" time RCL t LVCMOS data setup to CLKOUT RS t LVCMOS data hold from CLKOUT RH t LVCMOS data rise ...

Page 11

Timing Diagrams ■ LVCMOS LVCMOS output LVCMOS output load CLKOUT Rxn x=A,B,C,D,E n=0,1,2,3,4,5,6 ■ Phase-Locked Loop set time V DD RCLK +/- PD CLKOUT 80% 20% C =8pF RCP Figure–6 ...

Page 12

Data, Clock Input Timing Previous cycle RCLK + (Differential) RA+/- RA3 RA2 RB+/- RB3 RB2 RC+/- RC3 RC2 RD+/- RD3 RD2 RE+/- RE3 RE2 t RIP1 t RIP0 t RIP6 t RIP5 t RIP4 t RIP3 t RIP2 t ...

Page 13

Data, Clock Input and LVSMOS Output Timing LVDS Input RA6 RA5 RA4 RA+/- RB+/- RB6 RB5 RB4 RC6 RC5 RC4 RC+/- RD6 RD5 RD4 RD+/- RE6 RE5 RE4 RE+/- RCLK+/- LVCMOS Output CLKOUT (R/F=L) CLKOUT (R/F=H) RA0~6 RB0~6 RC0~6 ...

Page 14

... Power On Reset Power on reset is not mandatory for this device. (The PD pin should be set to high level when power on reset procedure is not used.) BU8255KVT However, Power on reset procedure is strongly recommend for internal logic initialization by following two methods. ① The method of using CR circuit. ...

Page 15

... LVDS Level Input & Output Example: BU8254KVT : LVCMOS level input/Falling edge/LVDS normal(350mV) swing output BU8255KVT : LVCMOS level output/Falling edge V DD VDD 0.1uF GND 0.01uF CLKIN CLKIN R4 TA0 R5 TA1 R6 TA2 R7 TA3 R8 TA4 R9 TA5 G4 TA6 G5 TB0 G6 TB1 G7 TB2 G8 TB3 G9 TB4 ...

Page 16

... Small Swing Input & LVCMOS Level Output Example: BU8254KVT : LVCMOS level input/Falling edge/LVDS normal(350mV) swing output BU8255KVT : LVCMOS level output/Falling edge V DD VDD 0.1uF GND 0.01uF CLKIN CLKIN R4 TA0 R5 TA1 R6 TA2 R7 TA3 R8 TA4 R9 TA5 G4 TA6 G5 TB0 G6 TB1 G7 TB2 ...

Page 17

TQFP64V TQFP64V <Dimension> 12.0 ± 0.3 10.0 ± 0 0.125 ± 0.1 0.2 ± 0.1 0.5 0.1 (Unit:mm) (Unit:mm) <Packing information> Container Tray(with dry pack) Quantity 1000pcs Direction Direction of product is ...

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