S1F78100Y2A Epson Electronics America, Inc., S1F78100Y2A Datasheet - Page 102

• Manufacturer Part Number: S1F78100Y2A
• Description: High Precision Voltage Regulators
• Manufacturer: Epson Electronics America, Inc.

Note 1 :
Note 2 :
Note 3 :
Note 4 :
S1F70000 Series
Technical Manual
V
G
Figure 8.4 shows 3 times step-up in the first stage and 4 times step-up in the next stage, but 4 times step-
DD
In case of series connection, the voltage V
Precautions on Load Connection
When a load is connected between GND in the first stage (or potential below GND in the second stage
other than that) and V
When a normal output is not available at the V
off V
other than that) to the V
absolute maximum rating below GND in the second stage may be generated at the V
result, the IC may not work normally. For series connection, connect the diode D1 between V
V
added to the V
up is possible both in the first stage and in the next stage unless the input voltage V
the specification value (6.0V). This means that each IC in this series connection is requested t satisfy the
specification values (V
2 times step-up in the first stage allows using the CAP- output in the first stage as the next stage clock,
but 3 times step-up does not. Attach an external R
Also, since the next stage external clock can operate according the CAP- output in the previous stage as
shown in Table 4.1 only when the temperature gradient C
same way when other temperature gradients are necessary.
stabilization circuit operates, has temperature gradient. This means that V
rate as temperature changes:
ND
REG
V
REG
T
REG
in the second stage as shown in Figure 8.4, so that no potential below GND in the second stage is
, current may flows from GND in the first stage (or potential below GND in the second stage
= C
V
Figure 8.5 Power Supply System in Series Connection
O
REG
T
(V
REG
pin.
REG
DD
’ (25˚C) – GND’)
REG
-GND 6, 0V, V
First stage Next stage
in the second stage as shown in Figure 8.4, pay attention to the following.
pin in the second stage through the load and a voltage higher than the
Max. 6.0V
EPSON
DD
O
-V
-GND 24V). (See Figure 8.5.)
REG
REG
V
G
DD
ND
pin at the starting time or when the P
'
(V
'
OSC
REG
as the next stage clock for internal oscillation.
T
’-V
is -0.6%/˚C, use the internal oscillator in the
V
O
DD
'
’ in Figure 8.5) of the IC, for which the
REG
changes at the following
S1F76640 Series
DD
’-GND’ exceeds
OFF
REG
V
REG
signal turns
pin. As a
'
DD
2–59
and