ADN2850 Analog Devices, Inc., ADN2850 Datasheet - Page 3

• Manufacturer Part Number: ADN2850
• Description: Nonvolatile Memory, Dual 1024 Position Programmable Resistors
• Manufacturer: Analog Devices, Inc.

Parameter
INTERFACE TIMING CHARACTERISTICS (apply to all parts)
FLASH/EE MEMORY RELIABILITY
NOTES
10
11
12
13
14
15
16
Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil
REV. B
1
2
3
4
5
6
7
8
9
Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.
Typicals represent average readings at 258C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I
Resistor terminals W and B have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V
Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.
P
Applies to photodiode of optical receiver.
All dynamic characteristics use V
See timing diagram for location of measured values. All input control voltages are specified with t
Switching characteristics are measured using both V
Propagation delay depends on value of V
Valid for commands that do not activate the RDY pin.
RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at T
and V
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
derate with junction temperature.
Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS to SDO – SPI Line Acquire
CS to SDO – SPI Line Release
CLK to SDO Propagation Delay
CS High Pulsewidth
CS High to CS High
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM
CS Rise to Clock Edge Setup
Preset Pulsewidth (Asynchronous)
Preset Response Time to Wiper Setting
Endurance
Data Retention
DISS
is calculated from (I
DD
< 3 V extends the save time to 35 ms.
15
16
DD
13
CYC
13
)
V
DD
DD
) + (I
= +2.5 V and V
DD
SS
12
, R
14
V
PULL_UP
SS
).
DD
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SS
DD
1
2
3
4
6
7
8
9
10
12
13
14
15
16
17
PRW
PRESP
, and C
= 5 V.
= –2.5 V.
, t
= 3 V and 5 V.
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will
5
103 mil, 10,197 sq mil.
L
. See Applications section.
Conditions
Clock Level High or Low
From Positive CLK Transition
From Positive CLK Transition
R
Applies to Command 2
Not Shown in Timing Diagram
PR Pulsed Low to Refresh
Wiper Positions
P
= 2.2 kΩ, C
–3–
5, 11
W
L
~ 50 µA for V
< 20 pF
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
H
, 3
H
DD
, 9
= 2.7 V and I
H
Min
20
10
1
10
5
5
10
4
0
10
50
100
W
~ 400 µA for V
DD
/2.
Typ
0.15
35
140
100
2
DD
= 5 V.
Max
40
50
50
0.3
ADN2850
Unit
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
t
ns
ms
ms
ns
ns
µs
K Cycles
Years
A
CYC
CYC
= –40°C