ADN2850 Analog Devices, Inc., ADN2850 Datasheet - Page 6

• Manufacturer Part Number: ADN2850
• Description: Nonvolatile Memory, Dual 1024 Position Programmable Resistors
• Manufacturer: Analog Devices, Inc.

ADN2850
Pin
No. Mnemonic Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDO
GND
V
V
W1
B1
B2
W2
V
V
WP
PR
CS
RDY
CLK
SDI
ADN2850BCP PIN FUNCTION DESCRIPTIONS
SS
1
2
DD
SDO
GND
V
Serial Data Output Pin. Open-Drain output
requires external pull-up resistor. CMD_9 and
CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of
multiple packages.
Ground Pin, logic ground reference
Negative Supply. Connect to zero volts for
single-supply applications.
Log Output Voltage 1 generated from internal
diode configured transistor
Wiper terminal of RDAC1 ADDR
(RDAC1) = 0
B terminal of RDAC1
B terminal of RDAC2
Wiper terminal of RDAC2. ADDR
(RDAC2) = 1
Log Output Voltage 2 generated from internal
diode configured transistor
Positive Power Supply Pin
Write Protect Pin. When active low, WP
prevents any changes to the present register
contents, except PR and CMD_1 and CMD_8
will refresh the RDAC register from EEMEM.
Execute a NOP instruction before returning
to WP high.
Hardware Override Preset Pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 512
a new value by the user (PR is activated at
the logic high transition).
Serial Register chip select active low.
Serial register operation takes place when
CS returns to logic high.
Ready. Active high open-drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
Serial Input Register Clock Pin. Shifts in
one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time
on positive clock CLK edges. MSB loaded first.
V
SS
1
1
2
3
4
ADN2850BCP
16
CHIP SCALE
5
PACKAGE
15 14 13
6
10
7
H
H
.
.
until EEMEM loaded with
8
12
11
10
9
PR
WP
V
V
DD
2
PIN CONFIGURATIONS
–6–
Pin
No. Mnemonic Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
SDI
SDO
GND
V
V
W1
B1
B2
W2
V
V
WP
PR
CS
RDY
ADN2850BRU PIN FUNCTION DESCRIPTIONS
SS
1
2
DD
GND
CLK
SDO
SDI
V
W1
Serial Input Register Clock Pin. Shifts in
one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at
a time on positive clock CLK edges.
MSB loaded first.
Serial Data Output Pin. Open-drain out put
requires external pull-up resistor. CMD_9
and CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of
multiple packages.
Ground Pin, logic ground reference
Negative Supply. Connect to zero volts for
single-supply applications.
Log Output Voltage 1 generated from internal
diode configured transistor
Wiper terminal of RDAC1. ADDR
(RDAC1) = 0
B terminal of RDAC1
B terminal of RDAC2
Wiper terminal of RDAC2. ADDR
(RDAC2) = 1
Log Output Voltage 2 generated from internal
diode configured transistor
Positive Power Supply Pin
Write Protect Pin. When active low, WP prevents
any changes to the present contents except PR
and CMD_1 and CMD_8 will refresh the
RDAC register from EEMEM. Execute a NOP
instruction before returning to WP high.
Hardware Override Preset Pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 512
new value by the user (PR is activated at the
logic high transition).
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
Ready. Active high open-drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
B1
SS
V
1
1
2
3
4
5
6
7
8
ADN2850BRU
(Not To Scale)
TOP VIEW
10
H
H
until EEMEM loaded with a
.
.
16
15
14
13
12
11
10
9
RDY
CS
PR
WP
W2
B2
V
V
DD
2
REV. B