ADN2530 Analog Devices, Inc., ADN2530 Datasheet - Page 15

• Manufacturer Part Number: ADN2530
• Description: 11.3 Gbps, Active Back-termination, Differential Vcsel Driver
• Manufacturer: Analog Devices, Inc.

APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 39 shows the typical application circuit for the
ADN2530. The dc voltages applied to the BSET and MSET pins
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 Ω resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 Ω transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 Ω differential (50 Ω
single-ended) transmission lines. Table 6 shows recommended
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at www.analog.com.
Table 6.
Component
R1, R2
R3, R4
C3, C4
L6, L7
L2, L3
L1, L4, L5, L8
Value
110 Ω
300 Ω
100 nF
160 nH
10 μH
DATAN
DATAP
MSET
BSET
+3.3V
Description
0603 size resistor
0603 size resistor
0402 size capacitor,
Phycomp 223878719849
0603 size inductor,
Murata LQW18ANR16
0603 size chip ferrite bead,
Murata BLM18HG601
0805 size inductor,
Murata LQM21FN100M70L
Z
Z
0
0
= 50Ω
= 50Ω
VCC
VCC
C1
C2
Figure 39. Typical ADN2530 Application Circuit
GND
C7
20μF
VCC
DATAP
DATAN
VCC
VCC
GND
BSET IBMON IBIAS GND
MSET
TP1
ADN2530
CPA
CPA
R5
750Ω
Rev. A | Page 15 of 20
ALS
ALS
GND
IMODN
IMODP
VCC
VCC
10nF
10nF
GND
C5
C6
GND
VCC
VCC
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see Figure 39. If proper decoupling cannot be
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 μF tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530, consult the
Amkor Technology® “Application Notes for Surface Mount
Assembly of Amkor’s Micro LeadFrame® (MLF®) Packages. ”
Z
Z
0
0
VCC
VCC
= 50Ω
= 50Ω
GND
GND
L1
L2
L3
L4
VCC
VCC
R1
R2
C4
C3
L5
L8
L7
L6
VCC
Z
Z
100nF
0
0
C8
= 50Ω
= 50Ω
R4
R3
V
CC
TOSA
ADN2530