CYP15G0401TB Cypress Semiconductor Corporation., CYP15G0401TB Datasheet - Page 17

• Manufacturer Part Number: CYP15G0401TB
• Description: Quad Hotlink Ii Transmitter
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02112 Rev. **
CYP15G0401TB AC Characteristics
Capacitance
t
t
CYP15G0401TB REFCLK Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
CYP15G0401TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
t
t
t
t
t
t
C
C
Notes:
19. While transmitting to a remote HOTLink II receiver the frequency difference between the transmitter and receiver reference clocks must be within ±1500-PPM.
20. The duty cycle specification is a simultaneous condition with the t
21. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.
22. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
23. Total jitter is calculated at an assumed BER of 1E –12. Hence: total jitter (t
24. Also meets all Jitter Generation requirements as specified by OBSAI RP3, CPRI, ESCON, FICON, Fibre Channel and DVB-ASI.
TXCLKOD+
TXCLKOD–
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
B
RISE
FALL
DJ
RJ
TXLOCK
INTTL
INPECL
Parameter
Parameter
[16, 21, 23]
While transmitting to an unknown remote receiver compliant to a particular standard, the stability of the crystal needs to be within the limits specified by the
appropriate standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.
cannot be as large as 30% – 70%.
range.
[16, 22, 23]
[19]
[16]
Parameter
[16]
[16, 17, 18]
[20]
[16, 17, 18]
[16]
TXCLKO+ Duty Cycle with 60% HIGH time
TXCLKO– Duty Cycle with 40% HIGH time
REFCLK Clock Frequency
REFCLK Period
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
Transmit Data Setup Time to REFCLK (TXCKSEL = LOW)
Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)
Bit Time
CML Output Rise Time 20% – 80% (CML Test
Load)
CML Output Fall Time 80% – 20% (CML Test
Load)
Deterministic Jitter (peak-peak)
Random Jitter (
Transmit PLL lock to REFCLK
TTL Input Capacitance
PECL input Capacitance
Description
σ
Description
)
Over the Operating Range (continued)
Description
PRELIMINARY
REFH
T
T
and t
A
A
= 25°C, f
= 25°C, f
J
REFL
) = (t
RJ
parameters. This means that at faster character rates the REFCLK duty cycle
* 14) + t
0
0
Test Conditions
= 1 MHz, V
= 1 MHz, V
SPDSEL = HIGH
SPDSEL = HIGH
SPDSEL = LOW
SPDSEL = LOW
SPDSEL = MID
SPDSEL = MID
IEEE 802.3z[
IEEE 802.3z
DJ
Condition
.
CC
CC
= 3.3V
= 3.3V
[24
24
]
]
2.9
2.9
5100
Min.
–1.0
–0.5
19.5
6.66
Min.
100
180
100
180
5.9
5.9
1.7
0.8
30
60
60
CYP15G0401TB
[16]
[16]
Max.
7
4
51.28
Max.
Max.
1000
1000
+0.5
+1.0
150
649
270
500
270
500
200
70
25
11
Page 17 of 30
2
2
Unit
pF
pF
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
us
%
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