T7256 Agere Systems, T7256 Datasheet - Page 57

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

Lucent Technologies Inc.
February 1998
Glossary
OUSCM:
PS1:
PS1E/TDMDO:
PS2:
PS2E/TDMCLK:
QMINT:
QMINTM:
QSC:
QSCM:
Q[4:1]:
R25R:
R25T:
R64T:
RESET:
RNR:
RPR:
RSFINT:
RSFINTM:
R[16:15]R:
R[16:15]T:
R[64:54:44:34]R:
(continued)
Other U-interface state change
mask (register UIR1, bit 3).
Power status #1 (register GR1,
bit 2).
Power status #1, TDM clock.
Power status #2 (register GR1,
bit 1).
Power status #2, TDM data out.
Quiet mode interrupt (register
MIR0, bit 0).
Quiet mode interrupt mask
(register MIR1, bit 0).
Q-bits state change (register
SIR0, bit 1).
Q-bits state change mask
(register SIR1, bit 1).
Q-channel bits (register MCR0,
bits 0—3).
Receive reserved bits
(register CFR2, bit 2).
Transmit reserved bit
(register CFR0, bit 4).
Transmit reserved bit
(register CFR0, bit 5).
Reset.
Receive negative rail for
S/T-interface.
Receive positive rail for
S/T-interface.
Receive superframe interrupt
(register UIR0, bit 4).
Receive superframe interrupt
mask (register UIR1, bit 4).
Receive reserved bits
(register CFR2, bits 1—0).
Transmit reserved bits
(register CFR0, bits 3—2).
Receive reserved bits
(register CFR2, bits 6—3).
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
SAI[1:0]:
SC1[4:1]:
SC2[4:1]:
SC3[4:1]:
SC4[4:1]:
SC5[4:1]:
SCK:
SDI:
SDINN:
SDINP:
SDO:
SFECV:
SFECVM:
SINT:
SIR0:
SIR1:
SOM:
SOMM:
SPWRUD:
SRESET:
STLED:
STOA:
Superframe:
S/T-interface activity indicator
control (register GR1, bits 6—7).
S subchannel 1 (register MCR1,
bits 0—3).
S subchannel 2 (register MCR2,
bits 0—3).
S subchannel 3 (register MCR3,
bits 0—3).
S subchannel 4 (register MCR4,
bits 0—3).
S subchannel 5 (register MCR5,
bits 0—3).
Serial interface clock.
Serial interface data input.
Sigma-delta A/D negative input
for U-interface.
Sigma-delta A/D positive input for
U-interface.
Serial interface data output.
S-channel far-end code violation
(register SIR0, bit 2).
S-subchannel far-end code viola-
tion mask (register SIR1, bit 2).
S/T-transceiver interrupt
(register GIR0, bit 1).
S/T-interface interrupt register.
S/T-interface interrupt mask
register.
Start of multiframe (register SIR0,
bit 0).
Start of multiframe mask
(register SIR1, bit 0).
S/T-interface powerdown control
(register GR2, bit 1).
S/T-interface reset (register GR2,
bit 2).
Status LED driver.
S/T-only activation (register GR2,
bit 7).
Eight U-frames grouped together.
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