MB15F03SL Fujitsu Media Devices, MB15F03SL Datasheet - Page 9

• Manufacturer Part Number: MB15F03SL
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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Table2. Binary 14-bit Programmable Reference Counter Data Setting
Table.3 Test Purpose Bit Setting
LSB
C
N
Note: Divide ratio less than 3 is prohibited.
1
1
H
H
Divide
T
1
L
L
16383
ratio
Programmable Counter
(R)
C
N
2
2
3
4
CNT1, 2 : Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW
FC
LDS
NOTE: Data input with MSB first.
D
S
IF/RF
3
L
IF/RF
IF/RF
W
4
S
H
H
T
2
L
L
: Divide ratio setting bits for the prescaler
: Phase control bit for the phase detector (IF: FC
: LD/fout signal select bit
14
R
0
0
1
IF/RF
(8/9 or 16/17 for the SW
C
5
F
6
A
1
13
R
0
0
1
7
A
2
12
R
0
0
1
8
A
3
LD/fout pin state
Outputs fp
Outputs fr
Outputs fp
11
Outputs fr
9
A
4
R
0
0
1
10 11 12 13 14 15 16 17 18 19 20 21 22 23
IF
A
5
, 64/65 or 128/129 for the SW
10
R
0
0
1
Data Flow
RF
A
IF
RF
6
IF
R
9
0
0
1
A
7
N
1
R
8
0
0
1
N
2
R
7
0
0
1
IF
, RF: FC
N
3
N
4
R
6
0
0
1
RF
)
RF
N
5
)
R
5
0
0
1
N
6
MB15F03SL
R
4
0
0
1
N
7
N
8
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
R
3
0
1
1
N
9
R
2
1
0
1
10
N
MSB
11
N
R
1
1
0
1
9