MB15F05L Fujitsu Media Devices, MB15F05L Datasheet - Page 8

• Manufacturer Part Number: MB15F05L
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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8
MB15F05L
Serial Data Input
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Shift Register Configuration
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
f
f
P:
N:
A:
f
R:
Note:
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL
VCO
VCO
OSC
CN1
:
:
H
H
= {(P x N) + A} x f
Programmable Reference Counter
Control bit
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (16 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 A
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
IF-PLL
LSB
C
N
1
1
CN1, 2
R1 to R14: Divide ratio setting bits for the programmable reference counter (5 to 16,383) [Table. 2]
T1, 2
X
NOTE: Data input with MSB first.
C
N
2
2
CN2
3
T
1
H
L
P = 16, N = 291, A = 7, R = 384, f
: Control bit
: Test purpose bit
: Dummy bits(Set "0" or "1")
OSC
T
4
2
5
R
1
R
The programmable reference counter for the RF-PLL.
The programmable counter and the swallow counter for the RF-PLL
R
6
2
(A < N)
R
3
7
R
8
4
9
R
5
10
R
6
11
R
7
Data Flow
12
R
8
OSC
Destination of serial data
13
R
9
= 19.2 MHz, f
14
10
R
15
11
R
127)
16
12
R
13
17
R
VCO
18
14
R
= 233.15 MHz, fr = 50 kHz (Fixed)
19 20 21 22 23
X
X
X
X
[Table. 1]
[Table.3]
MSB
X