MB81ES171625 Fujitsu Media Devices Limited, MB81ES171625 Datasheet
MB81ES171625
Related parts for MB81ES171625
MB81ES171625 Summary of contents
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... DESCRIPTION The Fujitsu MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 bit memory cells accessible 512K 16 bit / 2 256K 32 bit format. The MB81ES171625/173225 features a fully synchronous operation referenced to a positive edge clock same as that of SDRAM operation, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexist- ence ...
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... Single 1.8 V Supply 0.15 V tolerance • CMOS I/O interface • Programmable burst type, burst length, and CAS latency Burst type : Sequential Mode, Interleave Mode Burst length : full column ( bit bit) CAS latency MB81ES171625/173225-15 (Min t 30 ns, Max 33.3 MHz (Min t 15 ns, Max 66 ...
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... PAD LAYOUT MB81ES171625 MB81ES171625/173225-15-X DSE BME TBST DQC - - - - - - - - - - DDQ V SSQ DQM / CLK CKE V SSQ S16 V DDQ XCS XRAS XCAS XWE ...
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... MB81ES171625/173225-15-X MB81ES173225 4 PAD No.84 DSE BME TBST DQC DDQ V SSQ DDQ V SSQ DQM 2 DQM / ...
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... Auto Precharge Enable Address Input 12 0 CKE Clock Enable CLK Clock Input TBST BIST Control BME Burn In Enable DSE Disable DQC BIST Output S32 32 Select MB81ES171625/173225-15-X Function Row : Column : Function Row : Column : ...
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... MB81ES171625/173225-15-X BLOCK DIAGRAM MB81ES171625 CLK CLOCK BUFFER CKE S16 DSE BME COMMAND XCS DECODER XRAS XCAS XWE ADDRESS BUFFER/ A /AP 10 REGISTER & BA BANK SELECT DQM to DQM 1 0 I/O DATA BUFFER/ REGISTER TBST BIST DQC 6 To each block ...
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... BUFFER/ A /AP 10 REGISTER & BA BANK SELECT DQM to DQM 3 0 I/O DATA BUFFER/ REGISTER TBST BIST DQC MB81ES171625/173225-15-X To each block XRAS CONTROL SIGNAL XCAS LATCH XWE MODE REGISTER ROW ADDR. 13 COL. COLUMN ADDR. 5 ADDRESS COUNTER 32 BANK-1 BANK-0 FCRAM CORE (8,192 ...
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... MB81ES171625/173225-15-X FUNCTIONAL TRUTH TABLE 1. Command Truth Table Com- Function mand 1 Device Deselect * DESL No Operation * 1 NOP Burst Stop* 2 BST X16 Read * 3 READ X32 X16 Read with READA Auto-precharge * 3 X32 X16 3 Write * WRIT X32 X16 Write with WRITA 3 Auto-precharge * X32 Bank Active * 4 ACTV ...
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... DQM Truth Table Function Data Input/Output Enable Data Input/Output Disable V Valid, L Logic Low, H Logic High state at current clock cycle Notes : MB81ES171625; DQM and DQM 0 MB81ES173225; DQM , DQM respectively All commands assume no CSUS command on previous rising edge of clock. ...
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... MB81ES171625/173225-15-X 4. Operation Command Table (Applicable to single bank) Current XCS XRAS XCAS XWE State Idle Bank Active ...
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... Write with Auto precharge MB81ES171625/173225-15-X Addr Command X X DESL H X NOP L X BST H BA, CA, AP READ/READA L BA, CA, AP WRIT/WRITA H BA, RA ACTV L BA, AP PRE L AP PALL H X REF/SELF L MODE ...
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... MB81ES171625/173225-15-X Current XCS XRAS XCAS XWE State Precharging Bank Activating ...
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... Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down. All commands assume no CSUS command on previous rising edge of clock. All commands are assumed to be valid state transitions. All inputs are latched on the rising edge of the clock. MB81ES171625/173225-15-X XWE Addr Command X ...
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... MB81ES171625/173225-15-X 5. Command Truth Table for CKE CKE Current XCS XRAS XCAS XWE State (n-1) ( Self refresh Self- refresh Recovery ...
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... S16 should be held V , and S32 should be held V IH All entries in “COMMAND TRUTH TABLE FOR CKE” are specified at CKE (n) state and CKE input from CKE ( CKE (n) state must satisfy the corresponding setup and hold time for CKE. MB81ES171625/173225-15-X Addr Refer to “ ...
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... The program to the mode resister should be excuted after all banks are precharged. 2. FCRAM TM MB81ES171625/173225 utilizes FCRAM core technology. FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs. 3. Clock (CLK) and Clock Enable (CKE) All input and output signals of SDR I/F FCRAM use register type buffers ...
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... Next Stage Burst Read Burst Read Burst Read Burst Write Burst Write Burst Write Burst Write Burst Read Burst Read Precharge Burst Write Precharge MB81ES171625/173225-15 / (Min) is satisfied. (This parameter is reference only.) RCD is greater than t (Min RCD ...
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... MB81ES171625/173225-15-X (3) Counter Operation of Sequential Mode and lnterleave Mode Starting Column Address Burst Length 11. Full Column Burst and Burst Stop Command (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row ...
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... Program the mode register by Mode Register Set command (MRS addition recommended that DQM and CKE track V Register Set command (MRS) can be set before 2 Auto-refresh commands (REF possible to excute 5 before 4. MB81ES171625/173225-15-X after CKE brought high, and then the No operation command SI period. CKE should be held High ...
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... MB81ES171625/173225-15-X STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) MODE REGISTER SET CKE\(CSUS) BANK CKE ACTIVE SUSPEND WRIT CKE\(CSUS) WRITE WRITE SUSPEND CKE WRITA CKE\(CSUS) WRITE WITH WRITE SUSPEND CKE PRECHARGE PRE or PALL POWER ON POWER APPLIED Note: CKE\ means CKE goes Low-level from High-level. ...
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... SELFX t t REFC REFC *1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: Assume t (Min) is satisfied. RAS *4: Assume no I/O conflict. *5: Assume the last data has been appeared on DQ. Illegal Command. MB81ES171625/173225-15-X WRIT PRE READA WRITA t RSC RCD RCD ...
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... MB81ES171625/173225-15-X Minimum Clock Latency or Delay Time for Multi Bank Operation Second command (other MRS ACTV bank) First command MRS t t RSC RSC * 1 ACTV t RRD * READ READA WRIT WRITA BL DAL * PRE ...
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... * and Full Column are not applicable to the interleave mode. *2: A and are reserved for vender test MB81ES171625/173225-15 CAS Latency 5 ...
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... MB81ES171625/173225-15-X ABSOLUTE MAXIMUM RATINGS Parameter Voltage of V Supply Relative Voltage at Any Pin Relative Short Circuit Output Current Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ...
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... CAPACITANCE Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance MB81ES171625/173225-15-X Value Symbol Min Typ C 2.0 IN1 C 2.0 IN2 MHz Unit Max 5.0 pF 5 ...
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... MB81ES171625/173225-15-X DC CHARACTERISTICS Parameter Output High Voltage Output Low Voltage Input Leakage Current (Any Input) Output Leakage Current Operating Current (Average Power Supply Current) Power Supply Current (Precharge Standby Current) 26 (At recommended operating conditions unless otherwise noted.) Symbol Condition OH(DC ...
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... DC characteristics are measured after following “17. Power-Up Initialization” procedure in “ FUNCTIONAL DESCRIPTION”. I depends on output termination, load conditions, clock rate, number of address and/or command change DD within certain period. The specified values are obtained with the output open. MB81ES171625/173225-15-X Symbol Condition CKE 0 V, Any bank active, ...
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... MB81ES171625/173225-15-X AC CHARACTERISTICS (1) Basic AC Characteristics Parameter Clock Period Clock High Time * 1 Clock Low Time * 1 Input Setup Time * 1 Input Hold Time except for CKE * XRAS Access Time * 2 XCAS Access Time * Access Time from Clock (t Min Output in Low-Z * Output in High Output Hold Time * ...
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... Note: All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round whole number) . MB81ES171625/173225-15-X Symbol t ...
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... MB81ES171625/173225-15-X (4) Latency - Fixed Values Parameter CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay XCAS to XCAS Delay (Min) XCAS Bank Delay (Min) ...
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... Addr. & Data Output V OL Notes: Reference level of input/output signal is 0.9 V. Access time is measured at 0 characteristics are also measured in this condition. (7) Delay Time for Power Down Exit CLK CKE Command MB81ES171625/173225-15 0 1.4 V 0.9 V VALID 0 ...
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... MB81ES171625/173225-15-X (8) Pulse Width CLK Input (Control) COMMAND Notes : These parameters are a limit value of the rising edge of the clock from one command input to the next input. Measurement reference voltage is 0.9 V. (9) Access Time CLK XRAS t RCD XCAS DQ (Output ...
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... Clock Enable - Power Down Entry and Exit CLK CKE 1 * Command PD (NOP) NOP *1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2: The NOP command should be asserted in conjunction with CKE. *3: The ACTV command can be latched after t MB81ES171625/173225-15-X CSUS command ...
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... MB81ES171625/173225-15-X 3. Column Address to Column Address Input Delay CLK XRAS t RCD XCAS ROW Address ADDRESS Note : XCAS to XCAS delay ( 4. Different Bank Address Input Delay CLK t RRD XRAS XCAS ROW Address ADDRESS BA Bank 0 Note : XCAS Bank delay ( CBD 34 CCD (Min) (1 clock) CCD COLUMN ...
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... Input Mask and Output Disable CLK DQM (@ Read Read) DQM (@ Write Write Precharge Timing Applied to the Same Bank CLK Command ACTV Note : PRE means ‘PRE’ or ‘PALL’. MB81ES171625/173225-15 DQZ2 Q2 High-Z Q4 (same clock) DQD MASKED (Min) RAS PRE ...
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... MB81ES171625/173225-15-X 7. READ Interrupted by Precharge CLK Command DQ Command DQ Command DQ Command DQ Note : In case the In case the PRE means ‘PRE’ or ‘PALL’ Example @ PRE (2 clocks) ROH2 High-Z Q1 PRE (2 clocks) ROH2 Q1 Q2 PRE ROH2 clock. ROH is 2 clocks. ...
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... READ Interrupted by Burst Stop CLK Command ( Command ( WRITE Interrupted by Burst Stop (Example @ CLK Command DQ MB81ES171625/173225-15 Example @ BL Full Column BST (1 clock) BSH1 High BST (2 clocks) BSH2 BST Command Masked ...
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... MB81ES171625/173225-15-X 10. WRITE Interrupted by Precharge CLK Command DQ D Note : The precharge command (PRE) should be issued only after the t PRE means ‘PRE’ or ‘PALL’. 11. READ Interrupted by WRITE CLK Command READ DQM DQ *1: The First DQM makes high-impedance state (High-Z) between the last output and the first input data. ...
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... DQM DQ Notes: READ command should be issued after t The write data after READ command is masked by READ command. 13 READ with Auto Precharge Example @ CL CLK Command ACTV DQM DQ *: The Next ACTV command should be issued after BL MB81ES171625/173225-15 (Min) WR WRIT READ t (Max) CAC D3 D1 ...
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... MB81ES171625/173225-15-X 14. - WRITE with Auto Precharge CLK Command ACTV DQM DQ *: The Next command should be issued after (BL Notes: If the final data is masked by DQM, the precharge does not start at the clock of the final data input. Once the auto precharge command is asserted, no new command within the same bank can be issued ...
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... CKE should be held high for at least one t 17. Mode Register Set Timing CLK Command MRS Address MODE Note : The Mode Register Set command (MRS) should be asserted only after all banks have been precharged and High-Z. MB81ES171625/173225-15-X Exit (Min) * REFC SELFX * NOP * ...
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... MB81ES171625/173225-15-X ORDERING INFORMATION Part number MB81ES171625-15WFKT-X MB81ES173225-15WFKT-X 42 Configuration 512 K word 16 bit 2 bank 256 K word 32 bit 2 bank Shipping form Remarks wafer wafer ...
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... MB81ES171625/173225-15-X FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U ...