MB82D01171A Fujitsu Media Devices, MB82D01171A Datasheet

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MB82D01171A

Manufacturer Part Number
MB82D01171A
Description
16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory
Manufacturer
Fujitsu Media Devices
Datasheet

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FUJITSU SEMICONDUCTOR
MEMORY Mobile FCRAM
CMOS
16 Mbit (1 M word
Mobile Phone Application Specific Memory
MB82D01171A
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
Access Time (t
Active Current (I
Standby Current (I
Power Down Current (I
DESCRIPTION
The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This
MB82D01171A is suited for low power applications such as Cellular Handset and PDA.
PRODUCT LINEUP
PACKAGES
DATA SHEET
Parameter
AA
DDA1
Max, t
DDS1
Max)
Max)
DDP
CE
48-ball plastic FBGA
Max)
Max)
(BGA-48P-M16)
www.DataSheet4U.com
200 A 100 A 70 A 200 A 100 A 70 A 200 A 100 A 70 A
Fast Cycle Random Access Memory
80
CMOS 1,048,576-WORD
with Low Power SRAM Interface
-80/80L/80LL/85/85L/85LL/90/90L/90LL
80 ns
80L
80LL
16 bit)
TM
85
48-ball plastic FBGA
MB82D01171A
16 BIT
(BGA-48P-M18)
20 mA
10 A
85 ns
85L
85LL
90
DS05-11404-2E
90 ns
90L
90LL

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MB82D01171A Summary of contents

Page 1

... Mobile Phone Application Specific Memory MB82D01171A DESCRIPTION The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This MB82D01171A is suited for low power applications such as Cellular Handset and PDA. ...

Page 2

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL FEATURES • Asynchronous SRAM Interface • word 16 bit Organization • Fast Random Cycle Time : t RC • Fast Random Access Time : t • Low Power Consumption : I • Wide Operating Conditions : V T • Byte Write Control • 4 words Address Access Capability • ...

Page 3

... MB82D01171A PIN ASSIGNMENTS Flash Compatible FBGA (suffix PBT CE2 CE1 ...

Page 4

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL BLOCK DIAGRAM CE2 CE1 Address Row Latch & Decoder Buffer I/O Input Data Buffer Latch & Control Power Control Timing Control Memory Cell Array 16,777,216 bit Output ...

Page 5

... MB82D01171A FUNCTION TRUTH TABLE * Mode CE1 CE2 Power Down * Standby (Deselect Output Disable* Read Write L Write (Lower Byte) Write (Upper Byte Valid, L Logic Low, H Logic High Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. ...

Page 6

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL ABSOLUTE MAXIMUM RATINGS Parameter Voltage of V Supply Relative Voltage at Any Pin Relative Short Circuit Output Current Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ...

Page 7

... MB82D01171A PIN CAPACITANCE Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level V Power Down Current DD L Version LL Version L Version LL Version V Standby ...

Page 8

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) Parameter V Active Current DD Notes: All voltages are referenced to Vss. DC Characteristics are measured after following POWER-UP timing. I depends on the output load conditions. OUT 8 Symbol Conditions V V Max, DD(31 CE1 V and CE2 OUT ...

Page 9

... MB82D01171A 2. AC Characteristics (1) Read Operation Parameter Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z Address Setup Time to CE1 Low ...

Page 10

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (2) Write Operation Parameter Write Cycle Time Address Setup Time Address Hold Time CE1 Write Setup Time CE1 Write Hold Time WE Setup Time WE Hold Time LB and UB Setup Time LB and UB Hold Time OE Setup Time OE Hold Time OE High to CE1 Low Setup Time ...

Page 11

... MB82D01171A (3) Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit CE1 High Setup Time following CE2 High after Power Down Exit ...

Page 12

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL TIMING DIAGRAM 1. READ Timing #1 (OE Control Access) Address CE1 t CLOL OE t ASO DQ (Output) Note : CE2 and WE must be High for entire read cycle. 2. READ Timing #2 (CE1 Control Access) Address t ASC CE1 OE t CLZ DQ (Output) Note : CE2 and WE must be High for entire read cycle. ...

Page 13

... MB82D01171A 3. READ Timing #3 (Address Access after OE Control Access) Address Address Valid ( Address Address Valid ( ASO CE1 OE DQ (Output) Note : CE2 and WE must be High for entire read cycle. 4. READ Timing #4 (Address Access after CE1 Control Access) Address Address Valid ...

Page 14

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 5. WRITE Timing #1 (CE1 Control) Address CE1 (Input) Note : CE2 must be High for write cycle Address Valid OHCL t DS Valid Data Input WRC ...

Page 15

... MB82D01171A 6. WRITE Timing #2-1 (WE Control, Single Write Operation) Address t OHAH CE1 t OHCL OES OE t OHZ DQ (Input) Note : CE2 must be High for write cycle. -80/80L/80LL/85/85L/85LL/90/90L/90LL t WC Address Valid Valid Data Input ...

Page 16

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 7. WRITE Timing #2 (WE Control, Continuous Write Operation) Address t OHAH CE1 t OHCL (Input Address Valid OES t t OHZ DS Valid Data Input ...

Page 17

... MB82D01171A 8. READ/WRITE Timing #1-1 (CE1 Control) Address t CHAH CE1 OHCL OE t CHZ Read Data Output Note : Write address is valid from either CE1 last falling edge. -80/80L/80LL/85/85L/85LL/90/90L/90LL t WC Write Address ...

Page 18

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 9. READ/WRITE Timing #1-2 (CE1 Control) Address CE1 t WRC Min Write Data Input Note : The t is specified from the time satisfied both t OEH Read Address t ASC t WRC OEH t CLZ and t WRC ...

Page 19

... MB82D01171A 10. READ (OE Control) /WRITE (WE Control) Timing #2-1 Address t OHAH CE1 Low OES OE t OHZ Read Data Output Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE. -80/80L/80LL/85/85L/85LL/90/90L/90LL t WC Write Address ...

Page 20

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 11. READ (OE Control) /WRITE (WE Control) Timing #2-2 Address CE1 Low Write Data Input Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE Read Address Valid t ASO ...

Page 21

... MB82D01171A 12. POWER DOWN Timing CE1 CE2 t CSP DQ Power Down Entry 13. Standby Entry Timing after Read or Write CE1 t CHOX OE WE Active Read Note : Both t and t define the earliest entry timing for Standby mode. If either of timing is not satisfied, CHOX CHWX it takes t (Min) period from either last address transition ...

Page 22

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL 15. POWER-UP Timing 2 CE1 CE2 Note : The t specifies from CE2 Low to High transition after V C2HL CE1 must be brought to High prior to or together with CE2 Low to High transition C2HL CSP C2LP t C2HL V Min DD reaches specified minimum level. ...

Page 23

... MB82D01171A DATA RETENTION 1. Low V Characteristics DD Parameter V Data Retention Supply DD Voltage L Version LL Version V Data Retention DD Supply Current L Version LL Version Data Retention Setup Time Data Retention Recovery Time V Voltage Transition Time DD 2. Data Retention Timing t DRS 3 2.7 V CE2 2.1 V CE1 0 Data bus must be in High-Z at data retention entry. ...

Page 24

... ORDERING INFORMATION Part Number MB82D01171A-80PBT MB82D01171A-80LPBT MB82D01171A-80LLPBT MB82D01171A-85PBT MB82D01171A-85LPBT MB82D01171A-85LLPBT MB82D01171A-90PBT MB82D01171A-90LPBT MB82D01171A-90LLPBT MB82D01171A-80PBN MB82D01171A-80LPBN MB82D01171A-80LLPBN MB82D01171A-85PBN MB82D01171A-85LPBN MB82D01171A-85LLPBN MB82D01171A-90PBN MB82D01171A-90LPBN MB82D01171A-90LLPBN 24 Package 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0 ...

Page 25

... MB82D01171A PACKAGE DIMENSIONS 48-ball plastic FBGA (BGA-48P-M16) 9.00±0.10(.354±.004) INDEX AREA 0.20(.008 0.10(.004) 2000 FUJITSU LIMITED B48016S-1c-1 C -80/80L/80LL/85/85L/85LL/90/90L/90LL +0.15 1.05 –0.10 (Mounting height) +.006 .041 –.004 0.36±0.10 (Stand off) (.014±.004) 6.00±0.10 (4.00(.157)) (.236±.004) ...

Page 26

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) 48-ball plastic FBGA (BGA-48P-M18) 9.00 ± 0.10(.354 ± .004) INDEX AREA 0.20(.008 0.10(.004) S 2001 FUJITSU LIMITED B48018S-c-1 +0.15 1.05 –0.10 (Mounting height) +.006 .041 –.004 0.25 ± 0.10 (Stand off) (.010 ± .004) 6.00 ± 0.10 (3.75(.148)) (.236 ± .004) ...

Page 27

... MB82D01171A -80/80L/80LL/85/85L/85LL/90/90L/90LL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...

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