STE2002_06 ST Microelectronics, Inc., STE2002_06 Datasheet - Page 27
STE2002_06
Manufacturer Part Number
STE2002_06
Description
81 x 128 Single-chip LCD Controller/driver
Manufacturer
ST Microelectronics, Inc.
Datasheet
1.STE2002_06.pdf
(61 pages)
- Current page: 27 of 61
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STE2002
5.2
Figure 30. Communication protocol
Serial interface
The STE2002 serial Interface is a bidirectional link between the display driver and the
application supervisor.
It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one
for the peripheral enable (SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the
serial peripheral power consumption is zero. While SCE pin is high the serial interface is
kept in reset.
The STE2002 is always a slave on the bus and receive the communication clock on the
SCLK pin from the master.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the
positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C
=1);it is read on the eighth SCLK clock pulse during every byte transfer.
If SCE stays low after the last bit of a command/data byte, the serial interface expects the
MSB of the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM
and all the internal registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SOUT can be read only the driver I
that allows to read I
in steady state and during data write.
It is possible to short circuit DOUT and SDIN and read I2C address without any additional
lines.
WRITE MODE
S
S
READ MODE
SLAVE ADDRESS
0 1 1 1 1
0 1 1 1 1
S
A
S
A
1
1
STE2002 ACK
STE2002 ACK
S
A 0 A
0
S
A 1 A
0
R/W
R/W
2
C slave address is reported in Fig. 34 & 35. SOUT is in High impedance
Co
1 DC Control Byte
COMMAND WORD
STE2002 ACK
MASTER ACK
A
P
DATA Byte
SLAVE ADDRESS
STE2002 ACK
0 1 1 1 1
2
C slave address. The Command sequence
STE2002
A 0
Co
CONTROL BYTE
DC Control Byte
S
A
1
S
A
0
LAST
W
R
/
STE2002 ACK
A
C
o
D
C
CONTROL BYTE
MSB........LSB
0 0 0 0 0 0 A
N> 0 BYTE
DATA Byte
Bus interfaces
STE2002 ACK
A P
27/61
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