CMOS SDRAM Samsung Electronics, CMOS SDRAM Datasheet - Page 12

• Manufacturer Part Number: CMOS SDRAM
• Description: CMOS SDRAM Device Operations
• Manufacturer: Samsung Electronics

DEVICE OPERATIONS
8. Burst Stop & Interrupted by Precharge
9. MRS
*Note :
1) Normal Write
2) Write Burst Stop (BL=8)
4) Read Burst Stop (BL=4)
DQ(CL2)
DQ(CL3)
1
2. t
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively.
4. PRE : All banks precharge if necessary.
1) Mode Register Set
. SAMSUNG
DQM
CMD
CMD
MRS can be issued only at all banks precharge state.
CLK
CLK
Read or write burst stop command is valid at every burst length.
BL=4 & tRDL=1CLK
DQM
BDL
CMD
DQ
CLK
DQ
ELECTRONICS
CMD
: 1 CLK ; Last data in to burst stop delay.
CLK
can support t
WR
RD
WR
D
D
0
0
PRE
D
D
1
1
Note 4
RDL
STOP
D
tRP
Q
D
2
0
=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommands tRDL=2 CLK.
2
tRDL
PRE
D
Q
Q
D
3
Note 1
1
0
3
tBDL
MRS
1
STOP
D
Q
Note 2
4
1
2CLK
2
D
5
ACT
BL=4 & tRDL=2CLK
DQM
3) Read Interrupted by Precharge (BL=4)
CMD
CLK
DQ
DQ(CL2)
DQ(CL3)
CMD
CLK
WR
D
0
RD
D
1
D
2
tRDL
PRE
D
Q
Note 1
3
0
Rev. 0.2 Sep. 1999
CMOS SDRAM
PRE
Q
Q
1
0
1
Q
1
2