CMOS SDRAM Samsung Electronics, CMOS SDRAM Datasheet - Page 3

• Manufacturer Part Number: CMOS SDRAM
• Description: CMOS SDRAM Device Operations
• Manufacturer: Samsung Electronics

DEVICE OPERATIONS
D. DEVICE OPERATIONS
ADDRESSES of 16Mb
BANK ADDRESSES (BA)
: In case x 4
This SDRAM is organized as two independent banks of 2,097,152
words x 4 bits memory arrays. The BA inputs are latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank addresses BA are latched at bank
active, read, write, mode register set and precharge operations.
: In case x 8
This SDRAM is organized as two independent banks of 1,048,576
words x 8 bits memory arrays. The BA inputs are latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank addresses BA are latched at bank
active, read, write, mode register set and precharge operations.
: In case x 16
This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA inputs are latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank addresses BA
bank active, read, write, mode register set and precharge opera-
tions.
ADDRESS INPUTS (A0 ~ A10/AP)
: In case x 4
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A
The 11 bit row addresses are latched along with RAS and BA dur-
ing bank activate command. The 10 bit column addresses are
latched along with CAS, WE and BA during read or write com-
mand.
: In case x 8
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A
The 11 bit row addresses are latched along with RAS and BA dur-
ing bank activate command. The 9 bit column addresses are
latched along with CAS, WE and BA during read or write com-
mand.
: In case x 16
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A
The 11 bit row addresses are latched along with RAS and BA dur-
ing bank activate command. The 8 bit column addresses are
latched along with CAS, WE and BA during read or write com-
mand.
ELECTRONICS
0
~ BA
1
are latched at
0
0
0
~ A
~ A
~ A
10
10
10
/AP).
/AP).
/AP).
ADDRESSES of 64Mb
: In case x 4
This SDRAM is organized as four independent banks of
4,194,304 words x 4 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 8
This SDRAM is organized as four independent banks of
2,097,152 words x 8 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 16
This SDRAM is organized as four independent banks of
1,048,576 words x 16 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 4
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 12 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 8
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 16
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
BANK ADDRESSES (BA0 ~ BA1)
1
1
1
during bank activate command. The 10 bit column addresses
during bank activate command. The 9 bit column addresses
during bank activate command. The 8 bit column addresses
Rev. 0.2 Sep. 1999
CMOS SDRAM
0
0
0
~ BA
~ BA
~ BA
1
1
1
0
0
during read or
during read or
during read or
0
~ BA
~ BA
~ BA
0
0
0
1
1
1
0
0
0
~ A
~ A
~ A
inputs
inputs
inputs
~ BA
~ BA
~ BA
11
11
11
0
0
0
).
~
).
~
).
~
1
1
1