CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 13

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
5.2.3
5.2.4
5.2.4
5.2.5
5.2.6
5.2.7
5.3
5.3.1
 2002 CML Microsystems Plc
Filters
Digital filtering is applied to the data by two FIR filters. The first has 79 taps and provides stop
band rejection and sampling correction. This filter takes data from the modulator at the symbol
rate (18kHz) and interpolates to the sample rate (144kHz). The CMX981 has a mode that allows
data to be written directly to this filter at either rate. The second filter has 63 taps and provides the
primary Root Raised Cosine (RRC) shaping with a roll-off factor ( ) of 0.35. These filters contain
default coefficients at power up, but can be overwritten via the serial interface.
Gain Control
The amplitude of each channel can be adjusted independently. The gain multiplier provides a
resolution of 11 bits; i.e. the gain is adjustable in steps of 1/2048 of the maximum level. Additional
logic allows a mode of operation that will enable ramping up to the set signal level, stay at this
value while instructed by the user, then ramp down to zero.
Phase Pre-distortion
A further feature allows the user to compensate for non-orthogonal carrier phase in the external
quadrature modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q
channel signals to each other immediately prior to the DAC input.
Offset Adjustment
Offset registers allow any offsets introduced in the analogue sections of the transmit path to be
corrected digitally via the serial interface. The offset adjust is independently applied to each of the
I and Q channel. The adjustment range is plus and minus full scale. Thus care must be exercised
by the user to avoid excessive offsets being applied to the sigma-delta DAC.
Output Ramping
A facility is provided to allow ramping of the outputs in two modes. When enabled by the user, the
signal from the gain multiplier stage is multiplied by an envelope value. This value increments or
decrements at a rate programmed by the user. The ramping envelope can be selected by the user
to be linear or sigmoidal. A sigmoidal ramp will minimise spectrum spread while fast ramping is in
progress.
Sigma-Delta D-A Converters and Reconstruction Filters
The converters are designed to have low distortion and >80dB dynamic range. These 2nd order
converters operate at a frequency of 128x symbol rate so as to over-sample the data at their
inputs a further 16 times. The reconstruction filters are 3rd order, switched capacitor, low pass
filters designed to work in conjunction with an external RC.
Rx Data Path
Anti-Alias Filtering and Sigma-Delta A-D Converters
The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high over-sampling rate
relaxes the design requirements on the anti-alias filter. However, to achieve optimum
performance, the anti-alias filter must reject the sampling frequency to about -110dB, of which at
least 30dB must be provided externally. Additionally, in order to ease the complexity of the
subsequent digital filters, there is a further requirement that the anti-alias filter suppress 8x symbol
rate to about -125dB. The on-chip anti-alias filter can be by-passed and powered down, although
external anti-aliasing must then be provided. The fourth-order Sigma-Delta A-D converters are
designed to have low distortion and >90dB dynamic range. The baseband I and Q channels must
be provided as differential signal; this minimises in-band pick up both on and off the chip.
Both I and Q Sigma-Delta converters produce a single bit output sampled at MCLK/4. This data is
passed to a non-programmable decimation FIR filter, which is sampled at MCLK/4 and gives
sufficient rejection at 8x symbol rate (MCLK/64) to permit decimation to that frequency. Note that
around -30dB is provided by the primary anti-alias filters.
13
CMX981
D/981/1