CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 27

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
5.11.7 $09
5.11.8 $0A
5.11.9 $0B
 2002 CML Microsystems Plc
These values control the sampling point in the receive decimation filter. The values are 4-bit 2's
complement integers. The sampling point can therefore be adjusted by -8/16 to 7/16 of the sample
clock period.
Bit 7 indicates that the transmit path is active. The transmit path enable bit in the TxSetup register
should not be cleared until this bit is set low. An interrupt is generated when this bit is set low (if
unmasked in the Mask1 register).
Bit 6 is set high when a read occurs from an empty FIFO.
Bit 5 is set high when a write occurs to a full FIFO.
Bit 4 is set high when the FIFO contains one or more empty locations.
Bit 3 is set high when the FIFO contains three full locations and one empty location.
Bit 2 is set high when the FIFO contains one full location and three empty locations.
Bit 1 is set high when the FIFO is empty.
Bit 0 is set high when a status bit in this register causes an interrupt.
Bits 7 and 4 to 1 are only latched if the corresponding bit in the Mask1 register is unmasked.
Setting any of these bits high will unmask the corresponding interrupts in the Status1 register.
Bit
Bit
Bit
Transmit
Unmask
transmit
enable
enable
path
path
7
7
7
Q channel decimation filter sample delay
RxSetup2
Status1
Mask1
Unmask
under
under
FIFO
FIFO
read
read
6
6
6
FIFO over
FIFO over
Unmask
write
write
5
5
5
Receive Set-up Register 2
Status Register 1 (Read only)
Interrupt Mask Register 1
27
FIFO not
FIFO not
Unmask
full
full
4
4
4
nearly full
nearly full
Unmask
FIFO
FIFO
3
3
3
I channel decimation filter sample delay
Unmask
nearly
empty
nearly
empty
FIFO
FIFO
2
2
2
Unmask
empty
empty
FIFO
FIFO
1
1
1
FIFO IRQ
Not used.
Set low.
active
0
0
0
CMX981
D/981/1