CMX981 Consumer Microcircuits Limited, CMX981 Datasheet - Page 20

• Manufacturer Part Number: CMX981
• Description: Advanceddigital Radio Baseband Processor (tetra Etc.)
• Manufacturer: Consumer Microcircuits Limited

Advanced Digital Radio Baseband Processor
5.8.1
5.8.2
 2002 CML Microsystems Plc
Data Interlock Mechanisms
There are four possible transmission data interlock mechanisms. It is recommended that the user
always uses one of these methods.
Software polling requires the user to first check that the FIFO is not full before writing each TxData
word. This may be accomplished by inspecting the relevant FIFO status bits before writing one or
more data words.
The serial clock when ready mode is a hardware interlock mechanism. This mechanism allows the
user to write data words without doing any FIFO checks: the hardware handshake is implemented
by stopping the serial port clock when the FIFO is full. This mechanism should be used with care,
because stopping the clock will freeze all other serial port transfers, including access to the voice
codec, auxiliary data converters and receive data. Note that since the C-BUS interface is driven
from an external clock, it can still be used to access the CMX981.
Interrupt data demand is used to request data when the FIFO has reached a defined level. An
interrupt can be generated when the data in the FIFO reaches the level specified in the Status1
register.
The internally generated frame sync mode configures the TxFS pin as an output. Frame sync
pulses will appear on this pin while the transmit path is enabled and the FIFO is not full. In this
way, a hardware interlock mechanism is implemented without having to stop the serial clock.
Should a frame sync pulse be generated by the CMX981 before the user has data ready to
transmit to the FIFO, a read operation should be issued on the Tx port (MSB set low) that will be
ignored.
Direct Write to 79-tap Filter Mode
The FIFO and DQPSK modulator may be bypassed, allowing the user direct access to the Tx filter
chain input. The 79-tap filter is normally used to interpolate from the symbol rate to the sample
rate. However, in direct write mode, the user may select the input rate of the filter as either symbol
or sample rate.
Test Access to DAC Input
A mechanism to allow read and write access to DAC input data is provided for use in testing or in
other systems where the modulator and filter blocks are not required. In order to be able to write at
the sample rate, the serial clock must be set to MCLK. Alternatively, two or more serial ports have
to be used. Data written to the access points will be transferred to the DAC logic at the next
internal sample clock after the data is written to the register. Write operations to the upper and
lower byte register of I and Q channels must be synchronised in phase by the user to the internal
sample clock. This is to avoid splitting the I and Q channel or upper and lower bytes into different
samples. The internal sample clock can be programmed to appear on either the SymbolClock or
N_IRQ1 pins by programming the ConfigCtrl1 and IRQCtrl registers.
Note that data input at this point will have to be pre-filtered to compensate for the reconstruction
filter droop (approximately 2dB at MCLK/1024), which is normally compensated by the internal FIR
default coefficients.
Software polling
Serial clock when ready
Interrupt data demand
Internally generated frame sync
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CMX981
D/981/1