S1M1V045 Epson Electronics America, Inc., S1M1V045 Datasheet - Page 6

• Manufacturer Part Number: S1M1V045
• Description: Full CMOS Asynchronous SRAM
• Manufacturer: Epson Electronics America, Inc.

S1M1V045B0J7
6
Note :
Data retention timing (CS1 Control)
V
CS1
A0 to 17,SA
A0 to 17,SA
* : Reference data at Ta=25 C
DD
Data retention supply voltage
Data retention curren
Data hold time
Operation recovery time
Write Cycle 2 (CS2 Control)
I/O1 to 8
I/O1 to 8
Read Cycle
(Dout)
Timing Chart (Byte-mode)
CS1
DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
CS2
(Din)
(Dout)
CS2
CS1
WE
OE
*
*
*
1
2 In write cycle time that is controlled by C
3 When output buffer is in output state, be careful that do not input the opposite signals to the output data.
V
IL
During read cycle time, W
Parameter
2.4V
*1
t
0.8xV
CDR
DD
t
t
AS
t
t
CLZ1
ACS2
CLZ2
t
OLZ
t
t
ACC
ACS1
CS1
Data hold time
High-Z
V
t
AW
t
DDR
OE
t
RC
V
t
WC
t
Symbol
DD
–
t
CW2
1.2V
t
CW1
WP
V
I
t
t
–
DDR
CDR
R
*2, *3
– 0.2V
E
DDR
is to be "High" level.
t
DW
t
t
CHZ1
CHZ2
t
OHZ
0.8xV
t
t
OH
t
WR
DH
CS1 = CS2 V
2.4V
t
R
–
DD
–
S
–
1
or CS2, output buffer is to be "Hi-Z" state even if O
V
IL
V
Conditions
DDR
DD
A0 to 17,SA
A0 to 17,SA
I/O1 to 8
I/O1 to 8
Write Cycle 1 (CS1 Control)
Write Cycle 3 (WE Control)
– 0.2V or CS2 0.2V
(Dout)
(Dout)
= 2.5V
(Din)
(Din)
CS1
CS2
CS1
CS2
WE
WE
Data retention timing (CS2 Control)
V
CS2
DD
V
IH
0.3
2.4V
t
CDR
t
AS
t
AS
High-Z
t
AW
Min.
t
WHZ
100
1.2
CS2
Data hold time
–
0
t
V
*3
–
WC
t
WC
DDR
(V
t
–
t
*2, *3
t
t
E
CW2
CW2
CW1
CW1
t
WP
t
SS
WP
is "Low" level.
0.2V
1.2V
= 0V, Ta = –40 to 85 C)
Typ.*
t
t
DW
0.3
DW
–
–
–
t
t
WR
DH
t
t
WR
t
DH
OW
Max.
0.3
3.0
t
2.4V
9
–
–
R
Rev.1.0
Unit
V
ns
ns
V
IH
A