IDT82V2082 Integrated Device Technology, Inc., IDT82V2082 Datasheet - Page 37

• Manufacturer Part Number: IDT82V2082
• Description: 2Ch T1/J1/E1 Short Haul/long Haul Liu
• Manufacturer: Integrated Device Technology, Inc.

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.13 INTERRUPT HANDLING
When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active
low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 20H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
the INTM_GLB bit (GCF, 20H) is set to ‘0’, an active level on the INT pin
represents an interrupt of the IDT82V2082. The INT_CH[1:0] (GCF, 20H)
should be read to identify which channel(s) generate the interrupt.
Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt
can be enabled/disabled individually by the corresponding bit in the register
(INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corre-
sponding bit in the Status Register (STAT0, 16H...) or (STAT1, 17H...), and
the Interrupt Trigger Edge Selection Register can be used to determine how
the Status Register sets the Interrupt Status Register.
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (21H) will be reset. Only when all the pending
interrupt is acknowledged through reading the Interrupt Status Registers
Table-22 Interrupt Event
3.14 5V TOLERANT I/O PINS
TTL logic.
3.15 RESET OPERATION
•
Arbitrary Waveform Generator
Inband Loopback Deactivate Code Status
Synchronization Status of PRBS/QRSS
Inband Loopback Activate Code Status
All kinds of interrupt of the IDT82V2082 are indicated by the INT pin.
All the interrupt can be disabled by the INTM_GLB bit (GCF, 20H). When
The interrupt event is captured by the corresponding bit in the Interrupt
After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is
All digital input pins will tolerate 5.0
The chip can be reset in two ways:
Software Reset: Writing to the RST register (01H) will reset the chip
in 1 µs.
One-Second Timer Expired
Excessive Zeros Received
Code Violation Received
Error Counter Overflow
Driver Failure Detected
Equalizer Out of Range
JA FIFO Underflow
PRBS/QRSS Error
JA FIFO Overflow
Interrupt Event
LOS Detected
AIS Detected
TCLK Loss
Overflow
±
10% volts and are compatible with
(STAT0, STAT1)
TCLK_LOS
Status bit
IBLBA_S
IBLBD_S
PRBS_S
LOS_S
AIS_S
EQ_S
DF_S
37
Interrupt Status bit
(INTS0, INTS1)
TCLK_LOS_IS
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the
INTCH register (21H) be reset and the INT pin become inactive.
source for one channel:
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
•
flip-flops are reset, and all the registers are initialized to default values.
3.16 POWER SUPPLY
DAC_OV_IS
CNT_OV_IS
IBLBA_IS
IBLBD_IS
TMOV_IS
PRBS_IS
JAOV_IS
JAUD_IS
ERR_IS
LOS_IS
EXZ_IS
There are totally fourteen kinds of events that could be the interrupt
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13). Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-22
After reset, all drivers output are in high impedance state, all the internal
This chip uses a single 3.3 V power supply.
AIS_IS
EQ_IS
DF_IS
CV_IS
Hardware Reset: Asserting the RST pin low for a minimum of 100 ns
will reset the chip.
is a summary of all kinds of interrupt and the associated Status
Interrupt Edge Selection
IBLBD_IES
PRBS_IES
IBLBA_IES
TCLK_IES
LOS_IES
AIS_IES
(INTES)
EQ_IES
DF_IES
bit
TEMPERATURE RANGES
Interrupt Mask bit
(INTM0, INTM1)
DAC_OV_IM
TIMER_IM
IBLBA_IM
IBLBD_IM
PRBS_IM
JAOV_IM
JAUD_IM
TCLK_IM
ERR_IM
LOS_IM
EXZ_IM
CNT_IM
AIS_IM
EQ_IM
DF_IM
CV_IM
INDUSTRIAL