IDT82V2082 Integrated Device Technology, Inc., IDT82V2082 Datasheet - Page 55

• Manufacturer Part Number: IDT82V2082
• Description: 2Ch T1/J1/E1 Short Haul/long Haul Liu
• Manufacturer: Integrated Device Technology, Inc.

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-52 INTS1: Interrupt Status Register 1
4.2.10 COUNTER REGISTERS
Table-53 CNT0: Error Counter L-byte Register 0
Table-54 CNT1: Error Counter H-byte Register 1
DAC_OV_IS
CNT_OV_IS
CNT_H[7:0]
CNT_L[7:0]
TMOV_IS
JAOV_IS
JAUD_IS
Symbol
ERR_IS
Symbol
Symbol
EXZ_IS
CV_IS
(R, Address = 1AH, 3AH)
(R, Address = 1BH, 3BH)
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
7-0
7-0
Bit
Bit
Bit
6
2
0
7
5
4
3
1
Default
Default
Default
00H
00H
0
0
0
0
0
0
0
0
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event
= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: No JA Overflow interrupt event occurred
= 1: JA Overflow interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: No JA Underflow interrupt event occurred
= 1: JA Underflow interrupt event occurred
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: No PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: No Excessive Zeros interrupt event occurred
= 1: EXZ interrupt event occurred
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: No Code Violation interrupt event occurred
= 1: Code Violation interrupt event occurred
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: No One-Second Timer Expiration interrupt event occurred
= 1: One-Second Timer Expiration interrupt event occurred
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: No Counter Overflow interrupt event occurred
= 1: Counter Overflow interrupt event occurred
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
55
Description
Description
Description
TEMPERATURE RANGES
INDUSTRIAL
.