ACS21D Intersil Corporation, ACS21D Datasheet
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ACS21D
Manufacturer Part Number
ACS21D
Description
Radiation Hardened Dual 4-input And Gate
Manufacturer
Intersil Corporation
Datasheet
1.ACS21D.pdf
(2 pages)
Radiation Hardened Dual 4-Input AND Gate
The Radiation Hardened ACS21MS is a Dual 4-Input AND
Gate. For each gate, a HIGH level on all inputs results in a
HIGH level on the Y output. A LOW level on any input
results in a LOW level on the Y output. All inputs are
buffered and the outputs are designed for balanced
propagation delay and transition times.
The ACS21MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS21MS are
contained in SMD 5962-98629. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Ordering Information
Pinouts
5962F9862901VCC
ACS21D/SAMPLE-03
5962F9862901VXC
ACS21K/SAMPLE-03
5962F9862901V9A
ORDERING NUMBER
GND
NC
A1
B1
C1
D1
Y1
1
2
3
4
5
6
7
TOP VIEW
ACS21MS
(SBDIP)
1
ACS21DMSR-03
ACS21D/SAMPLE-03
ACS21KMSR-03
ACS21K/SAMPLE-03
ACS21HMSR-03
INTERNAL MARKETING
Data Sheet
14
13
12
11
10
9
8
V
D2
C2
NC
B2
A2
Y2
CC
NUMBER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
TEMP. RANGE (
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
• Input Logic Levels. . . . V
• Output Current
• Quiescent Supply Current . . . . . . . . . . . . . . . 5.0 A (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 15ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
-55 to 125
-55 to 125
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
- SEU Immunity . . . . . . . . . . . . . <1 x 10
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
GND
25
25
25
NC
A1
B1
C1
D1
Y1
o
C)
July 1999
14 Ld SBDIP
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
(FLATPACK)
1
2
3
4
5
6
7
PACKAGE
TOP VIEW
ACS21MS
IL
= (0.3)(V
File Number
14
13
12
11
10
9
8
CC
ACS21MS
), V
-10
CDIP2-T14
CDIP2-T14
CDFP3-F14
CDFP3-F14
NA
DESIGNATOR
IH
Errors/Bit/Day
= (0.7)(V
12mA (Min)
5
RAD(Si)
V
D2
C2
NC
B2
A2
Y2
4757
CC
CC
2
)
)