ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 77

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Figure 16 Recommended Line Termination for LVDS Input Ports
DC Characteristics: AMI Input/Output Port
(Across all operating Conditions, unless otherwise stated.)
The Alternate Mark Inversion (AMI) signal is DC balanced
and consists of positive and negative pulses with a peak-
to-peak voltage of 2.0 ±0.2 V.
The electrical specifications are taken from option a) of
Table 2/G.703 - Digital 64 kbit/s centralized clock
interface, from ITU G.703
The electrical characteristics of the 64 kbits/s interface
are as follows:
Nominal bit rate: 64 kbits/s. The tolerance is determined
by the network clock stability.
Revision 3.00 April 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
[6]
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FINAL
There should be a symmetrical pair carrying the composite
timing signal (64 kHz and 8 kHz). The use of transformers
is recommended.
Over-voltage
Recommendation K.41[15]
Code conversion rules:
The data signals are coded in AMI code with 100% duty
cycle. The composite clock timing signals convey the 64
kHz bit-timing information using AMI coding with a 50% to
70% duty ratio and the 8 kHz octet phase information by
introducing violations in the code rule. The structure of the
signals and voltage level are shown in Figure 17 , Figure
18 and Figure 19 .
protection
ACS8514 SETS Buddy
requirement:
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