ACS8944 Semtech Corporation, ACS8944 Datasheet

ACS8944

Manufacturer Part Number

ACS8944

Description

Jitter Attenuating, Multiplying Phase Locked Loop for Oc-12/stm-4

Manufacturer

Semtech Corporation

Datasheet

1.ACS8944.pdf (24 pages)

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The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying

Phase-Locked Loop, for generating low jitter output clocks

compliant up to SONET OC-12 and STM-4 622.08 MHz

specifications. Its primary function is to clean up clock

jitter for high performance optical line cards which have

OC-3 or OC-12 SONET serializers or framers, and is the

entry level device in Semtech’s range of JAM PLLs.

The ACS8944 JAM PLL has a single differential LVPECL

input and a single differential LVPECL output. Both input

and output clock frequencies are individually

programmable and can be hardware configured to be any

of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz.

The headline jitter figures quoted for the ACS8944

depend on the frequency band over which the jitter is

measured. For example, typical stand-alone output jitter

is typically 2.8 ps rms (well within GR-253-CORE

specification requirements of 16.1 ps rms for OC-12 and

64.3 ps rms for OC-3).

The device's operating bandwidth (and consequently the

jitter attenuation point relating to this bandwidth) is set by

external passive components in a differential

arrangement which offers good noise immunity.

Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL

Revision 3/November 2006 © Semtech Corp.

Introduction

ADVANCED COMMUNICATIONS

Block Diagram

ADVANCED COMMUNICATIONS

Differential

Input Reference

LVPECL

155.52 MHz

77.76 MHz

38.88 MHz

19.44 MHz

LVPECL

RESETB

Frequency

Divider

Control and Monitor

Charge

[8]

Pump

PFD

FINAL

Jitter Attenuating, Multiplying Phase Locked Loop

Page 1

Loop

Filter

Note...For items marked

in the Reference Section on page 21.

Features

Meets rms jitter requirements of:

Typical jitter generation down to:

• 0.3 ps rms for 250 kHz to 5 MHz band for G.813,

• 2.8 ps rms for 12 kHz to 20 MHz band (against

Pull-in range ±400 ppm about center input frequency

Frequency translation e.g. 19.44 MHz to 155.52 MHz

3.3 V operation, - 40 to +85°C temperature range

Small outline leadless 7 mm x 7 mm QFN48 package

Demonstration Board available on request

PLL bandwidth and jitter peaking are fully adjustable.

Supports bandwidths from 2 kHz for superior input

jitter filtering

Lead (Pb)-free version available (ACS8944T), RoHS

and WEEE

2.5 GHz

VCO

Telcordia GR-253-CORE

ITU-T G.813

ETSI EN300-462-7

rates

or EN300-462, at STM-4 (OC-12) rates

4.02 ps rms for GR-253-CORE at OC-48 rate)

[10]

compliant

Frequency

[4]

Divider

/G.812

ACS8944 JAM PLL

[1],[2], etc.

[1]

/EN302-084

[3]

[8]

for STM-1 and STM-4 rates

LVPECL

references are given in full

for OC-3 and OC-12

for OC-12/STM-4

[2]

DATASHEET

www.semtech.com

F8944D_001Blockdiag_02

up to STM-16

Differential

Clock Output

LVPECL

155.52 MHz

77.76 MHz

38.88 MHz

19.44 MHz

[9]

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