L64733 LSI Logic Corporation, L64733 Datasheet - Page 39

• Manufacturer Part Number: L64733
• Description: Tuner/receiver Chipset
• Manufacturer: LSI Logic Corporation

The numbers in the first column of
parameters shown in the preceding figures. All parameters in the timing
tables apply for T
Table 11
1. Minimum Fs (sampling clock = 30 MHz).
L64733/L64734 Tuner and Satellite Receiver Chipset
Parameter
10
11
12
13
1
2
3
4
5
6s t
6p t
7
8
9
t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
PWH
PWL
S
H
ODS
ODP
RWH
WK
DLY
CYCLE_PS
PWH_PS
PWL_PS
OD_PS
L64734 AC Timing Parameters
Description
Clock Cycle for PCLK
Clock Pulse Width HIGH
Clock Pulse Width LOW
Input Setup Time to CLK
Input Hold to CLK
Output Delay from PCLK, serial mode
Output Delay from BCLKOUT, parallel
mode
Reset Pulse Width HIGH
Wake-Up Time
Delay from COEn
Clock Cycle for PSOUTp, PSOUTn
clock
PSOUT Clock Pulse Width HIGH
PSOUT Clock Pulse Width LOW
Output Delay from PSOUT
A
= 0 ˚C to 70 ˚C and a capacitive load of 15 pF.
Table 11
refer to the timing
Min
11.1 33.3
280
14
6
5
4
4
3
3
3
–
6
6
4
Max
8.5
35
–
–
–
–
8
–
–
–
6
–
–
1
Units
cycles
cycles
cycles
PCLK
CLK
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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