L64733C LSI Logic Corporation, L64733C Datasheet - Page 12

• Manufacturer Part Number: L64733C
• Description: Tuner And Satellite Receiver Chipset Data Sheet 2/01
• Manufacturer: LSI Logic Corporation

12
FDOUB
FLCLK
IDCp, IDCn
INSEL
LOBUF
L64733C/L64734 Tuner and Satellite Receiver Chipset
Frequency Doubler
When FDOUB is asserted, the L64733C local oscillator
frequency is internally doubled and fed to the mixers.
When FDOUB is deasserted, the oscillator frequency is
not doubled before being fed to the mixers.
Bit 6 of register 79, group 4 (APR 79), controls the
L64734 FDOUB output pin, which enables or disables the
frequency doubler on the L64733C.
The FDOUB pin is set as shown in the table below, where
F
enabled or disabled.
Frequency
925 MHz–F
F
1680–2175 MHz
This method of control preserves the compatibility with
the L64733B, which is not affected by 3-stating the
FDOUB pin.
Filter Clock
The FLCLK signal is a low amplitude, self-biased clock
input. The frequency of the FLCLK signal multiplied by 16
is the baseband filter’s 3 dB frequency.
I-Channel DC Offset Correction
Connect a 0.1 F or larger capacitor between the IDCp
and IDCn signals.
RF Port Input Select
When the INSEL signal is asserted, the L64733C is in
normal mode. When the INSEL signal is deasserted, the
L64733C is in Loop-Through mode. In this mode, the
RFIN signal is looped through out to the RFOUT signal
and the L64733C local oscillator is shut off.
Local Oscillator Buffer Select
Asserting LOBUF causes the external PLL mode to be in
effect, the local oscillator (LO) buffer to be enabled, and
the LO signal to be sent out to the PSOUT pins according
to the division ratio selected with the LODIV signal. When
switch
switch
–1680 MHz
is the frequency at which the frequency doubler is
switch
APR 79[6]
FDOUB
0
1
1
APR 79[2]
TRI
0
1
0
FDOUB
3-state
HIGH
LOW
Pin
Input
Input
Input
Input
Input