L64733C LSI Logic Corporation, L64733C Datasheet - Page 21

• Manufacturer Part Number: L64733C
• Description: Tuner And Satellite Receiver Chipset Data Sheet 2/01
• Manufacturer: LSI Logic Corporation

MODp, MODn Modulus Selector
PLLINp, PLLINn
PSOUTp, PSOUTn
RESO_LVDS LVDS Buffers Precision Resistor
L64733C/L64734 Tuner and Satellite Receiver Chipset
The FDOUB pin is set as shown below; F
frequency that disables or enables the frequency doubler.
Frequency
925 MHz–F
F
1680–2175 MHz
The MODp and MODn signals are low-voltage differential
signals from the L64734 of modulus selector
programmable counter (A). PSOUT clocks these signals.
When the MODp signal is positive with respect to the
MODn signal, divide-by-32 is selected at the dual
modulus prescaler on the L64733C Tuner IC. When
MODp is negative with respect to MODn, divide-by-33 is
selected. The counter A can be programmed to count
down from a particular value by register bit programming.
PLL Differential Counter M
The PLLINp and PLLINn signals are low-voltage
differential signals from the L64734 programmable
synthesizer counter (M). PSOUT clocks these signals.
PLLINp is positive with respect to PLLINn for one PSOUT
cycle. The repetition rate is 0.5 MHz for a 4 MHz
reference crystal. The counter M can be programmed to
count down from a particular value by register bit
programming.
Prescaler Output
The PSOUTp and PSOUTn signals are differential
signals to the L64734 from the L64733C. The
programmable counters on the L64734 are clocked on
the rising edge of the PSOUT signal.
In the external PLL mode (LOBUF = HIGH), these signals
come from the LO buffer, for which the LODIV signal sets
the divider ratio.
The RESO_LVDS output must be connected to a resistor
(6.8 k , which controls the swing of the LVDSOUT
switch
–1680 MHz
switch
APR 79[6]
FDOUB
0
1
1
APR 79[2]
TRI
0
1
0
switch
FDOUB
3-state
is the
HIGH
LOW
Pin
Output
Output
Output
Output
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