AD9854 Analog Devices, AD9854 Datasheet - Page 17

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Mode
Single-Tone
FSK
Ramped FSK
CHIRP
BPSK
Differential REFCLK Enable
A high level on this pin enables the differential clock Inputs,
REFCLOCK and REFCLOCKB (Pins 69 and 68 respec-
tively). The minimum differential signal amplitude required
is 800 mV p-p. The centerpoint or common-mode range of the
differential signal can range from 1.6 V to 1.9 V.
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK
(Pin 69) is the only active clock input. This is referred to as
the single-ended mode. In this mode, Pin 68 (REFCLKB) should
be tied low or high, but not left floating.
Parallel/Serial Programming Mode
Setting Pin 70 high invokes parallel mode, whereas setting Pin
70 low will invoke the serial programming mode. Please refer to
the text describing the serial and parallel programming proto-
col contained in this data sheet for further information.
Two control bits located at address 20 hex in the Table V apply
only to the serial programming mode. LSB First when high,
dictates that serial data will be loaded starting with the LSB of
the word. When low (the default value), serial data is loaded
starting with the MSB of the word. SDO Active when high indi-
cates that the SDO pin, Pin 18, is dedicated as an output to read
back data from the AD9854 registers. When SDO Active is low
(default value), this indicates that the SDIO pin, Pin 19, acts as
a bidirectional serial data input and output pin and Pin 18 has
no function in the serial mode.
DESCRIPTION OF AD9854 MODES OF OPERATION
There are five programmable modes of operation of the AD9854.
Selecting a mode requires that three bits in the Control Register
(parallel address 1F hex) be programmed as follows in Table II.
REV. 0
Phase
Adjust 1
MODE
TW1
Phase
Adjust 2
X
X
X
X
000 (DEFAULT)
F1
0
Figure 35. Default State to User-Defined Output Transition
Single-Pin
FSK/BPSK
or HOLD
X
0
Table III. Function Availability vs. Mode of Operation
Single-Pin
Shaped-
Keying
Phase
Offset or
Modulation
X
–17–
000 (SINGLE TONE)
Mode 2
0
0
0
0
1
In each mode, engaging certain functions may or may not be
permitted. Shown in Table III is a listing of some important
functions and their availability for each mode.
Single-Tone (Mode 000)
This is the default mode when master reset is asserted or when
it is user-programmed into the control register. The Phase
Accumulator, responsible for generating an output frequency, is
presented with a 48-bit value from Frequency Tuning Word 1
registers whose default values are zero. Default values from the
remaining applicable registers will further define the single-tone
output signal qualities.
The default values after a master reset, define a safe, “no output”
value resulting in an output signal of 0 Hertz, 0 phase. Upon
power-up and reset the output from both I and Q DACs will be
a dc value equal to the midscale output current. This is the
default mode amplitude setting of zero. Refer to the digital multi-
plier section for further explanation of the output amplitude
control. It will be necessary to program all or some of the 28
program registers to realize a user-defined output signal.
Figure 35 graphically shows the transition from the default con-
dition (0 Hz) to a user defined output frequency (F1).
As with all Analog Devices DDSs, the value of the frequency
tuning word is determined using the following equation:
F1
Amplitude
Control or
Modulation
FTW = (Desired Output Frequency 2
Mode 1
0
0
1
1
0
Table II. Mode Selection Table
Inverse
SINC
Filter
Frequency
Tuning
Word 1
Mode 0
0
1
0
1
0
Frequency Automatic
Tuning
Word 2
X
X
X
N
Result
SINGLE-TONE
FSK
RAMPED FSK
CHIRP
BPSK
)/SYSCLK.
AD9854
Frequency
Sweep
X
X
X