AD9854 Analog Devices, AD9854 Datasheet - Page 36

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

AD9854
Observing the Unfiltered IOUT1 and the Unfiltered IOUT2
DAC Signals
This allows the viewer to observe the unfiltered DAC outputs at
J2 (the “I” signal) and J1 (the “Q” signal). The procedure below
simply routes the two 50
the BNC connectors and disconnects any other circuitry. The
“raw” DAC outputs will be a series of quantized (stepped) output
levels. The default 10 mA output current will develop a 0.5 V p-p
signal across the on-board 50
to an external 50
due to the double termination.
1. Install shorting jumpers at W7 and W10.
2. Remove shorting jumper at W16.
3. Remove shorting jumper from 3-pin header W1.
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
Observing the Filtered IOUT1 and the Filtered IOUT2
This allows viewer to observe the filtered I and Q DAC outputs
at J4 (the “I” signal) and J3 (the “Q” signal). This places the
50
pathways to remove images and aliased harmonics and other
spurious signals above the dc to approximately 120 MHz band-
pass. These signals will appear as nearly pure sine waves and
exactly 90 degrees out-of-phase with each other. These filters
are designed with the assumption that the system clock speed is
at or near maximum (300 MHz). If the system clock utilized is
much less than 300 MHz, for example 200 MHz, unwanted DAC
products other than the fundamental signal will be passed by the
low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
Observing the Filtered I
This allows viewer to observe only the filtered “I” DAC outputs
at J4 (the “true” signal) and J3 (the “complementary” signal).
This places the 120 MHz low pass filters in the true and comple-
mentary output paths of the I DAC to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These signals will appear as nearly pure sine waves
and exactly 180 degrees out-of-phase with each other. Again, if
the system clock used is much less than 300 MHz, for example
200 MHz, then unwanted DAC products other than the funda-
mental signal will be passed by the low-pass filters.
3-pin header W4.
3-pin header W1.
3-pin header W4.
pin header W2 and W8.
(input and output Z) low-pass filters in the I and Q DAC
input, the DAC will therefore develop 0.25 V p-p
OUT
terminated analog DAC outputs to
and the Filtered I
termination. When connected
OUT
B
–36–
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
4. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
To connect the high-speed comparator to the DAC output sig-
nals choose either the quadrature filtered output configuration
or the complementary filtered output configuration as outlined
above. Follow Steps 1 through 4 above, for the desired filtered
configuration. Step 5 below will reroute the filtered signals away
from their connectors (J3 and J4) and connect them to the 100
configured comparator inputs. This configures the comparator
for differential input without control of the comparator output
duty cycle. The comparator output duty cycle should be approxi-
mately 50% in this configuration.
5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of
User may elect to change the R
2 k to get a more robust signal at the comparator inputs. This
will decrease jitter and extend comparator operating range. This
can be accomplished by soldering a second 3.9 k chip resistor
in parallel with the provided R2.
Connecting the High-Speed Comparator in a Single-Ended
Configuration
This will allow duty cycle or pulse width control and requires that a
dc threshold voltage be present at one of the comparator inputs.
You may supply this voltage using the “Q DAC” by configuring
it as a control DAC in software or by removing the shorting jumper
at 2-pin header W6. A 12-bit, twos-complement value is written
to the Q-DAC register that will set the IOUT2 output to a static
dc level. Allowable hexadecimal values are 7FF (maximum) to
800 (minimum) with all 0s being midscale. The IOUT1 channel
will continue to output a filtered sine wave programmed by the
user. These two signals are routed to the comparator inputs
using W2 and W8 3-pin header switches. The configuration
described above entitled “Observing the Filtered I
Filtered I
then the following Step 5:
5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of
User should elect to change the R
1950
This will decrease jitter and extend comparator operating range.
User can accomplish this by soldering a second 3.9 k chip
resistor in parallel with the provided R2.
pin header W1.
pin header W4.
pin header W2 and W8.
3-pin header W2 and W8.
3-pin header W2 and W8.
to get a more robust signal at the comparator inputs.
OUTB
” must be used. Follow Steps 1 through 4 and
SET
resistor, R2 from 3.9 k to
SET
resistor from 3900
OUT
and the
REV. 0
to