AD9854 Analog Devices, AD9854 Datasheet - Page 2

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Parameter
REF CLOCK INPUT CHARACTERISTICS
DAC STATIC OUTPUT CHARACTERISTICS
DAC DYNAMIC OUTPUT CHARACTERISTICS
AD9854–SPECIFICATIONS
REFCLK Multiplier enabled at 10 for AD9854ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 10
AD9854AST unless otherwise noted.)
Internal Clock Frequency Range
External REF Clock Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
Differential Mode Common-Mode Voltage Range
V
V
Output Update Speed
Resolution
I and Q Full-Scale Output Current
I and Q DAC DC Gain Imbalance
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
I and Q DAC Quad. Phase Error
DAC Wideband SFDR
DAC Narrowband SFDR
Residual Phase Noise
Pipeline Delays
IH
IL
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
Minimum Signal Amplitude
Common-Mode Range
1 MHz to 20 MHz A
20 MHz to 40 MHz A
40 MHz to 60 MHz A
60 MHz to 80 MHz A
80 MHz to 100 MHz A
100 MHz to 120 MHz A
10 MHz A
10 MHz A
10 MHz A
41 MHz A
41 MHz A
41 MHz A
119 MHz A
119 MHz A
119 MHz A
(A
REFCLK Multiplier Engaged at 10 )
(A
REFCLK Multiplier Bypassed)
Phase Accumulator and DDS Core
Inverse Sinc Filter
Digital Multiplier
(Single-Ended Mode)
(Single-Ended Mode)
1 kHz Offset
10 kHz Offset
100 kHz Offset
1 kHz Offset
10 kHz Offset
100 kHz Offset
OUT
OUT
= 5 MHz, Ext. CLK = 30 MHz,
= 5 MHz, Ext. CLK = 300 MHz,
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
( 1 MHz)
( 250 kHz)
( 50 kHz)
( 1 MHz)
( 250 kHz)
( 50 kHz)
( 1 MHz)
( 250 kHz)
( 50 kHz)
OUT
OUT
OUT
OUT
OUT
OUT
2
1
Temp
FULL
FULL
FULL
25 C
25 C
25 C
25 C
25 C
25 C
25 C
FULL
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
(V
S
= 3.3 V
Test
Level
VI
VI
VI
IV
IV
IV
IV
IV
IV
IV
I
IV
IV
I
I
I
I
I
IV
I
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IV
IV
IV
–2–
5%, R
Min
5
5
5
45
800
1.6
2.3
5
–0.5
–6
–0.5
SET
AD9854ASQ
= 3.9 k
Typ
50
3
100
1.75
12
10
+0.15
0.3
0.6
100
0.2
58
56
52
48
48
48
83
83
91
82
84
89
71
77
83
140
138
142
142
148
152
17
12
10
Max
300
75
300
55
1.9
1
300
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
external reference clock frequency = 30 MHz with
Min
5
5
5
45
800
1.6
2.3
5
–0.5
–6
–0.5
AD9854AST
Typ
50
3
100
1.75
12
10
+0.15
0.3
0.6
100
0.2
58
56
52
48
48
83
83
91
82
84
89
140
138
142
142
148
152
17
12
10
Max
200
50
200
55
1.9
1
200
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
Unit
MHz
MHz
MHz
%
pF
k
mV p-p
V
V
V
MSPS
Bits
mA
dB
% FS
LSB
LSB
k
V
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
SysClk Cycles
SysClk Cycles
SysClk Cycles
A
REV. 0
for