MAX108 Maxim, MAX108 Datasheet - Page 14

• Manufacturer Part Number: MAX108
• Description: 5V / 1.5Gsps / 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
• Manufacturer: Maxim

REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally connected to GNDR. GNDR
must be connected to GNDI on the user’s application
board. If required, REFOUT can source up to 2.5mA to
supply external devices.
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer-
ence supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT must not be simultaneously
connected, to avoid conflicts between the two refer-
ences. REFIN has a typical input resistance of 5kΩ and
accepts input voltages of +2.5V ±200mV. For best per-
formance, Maxim recommends using the MAX108’s
internal reference.
The MAX108 provides data in offset binary format to
differential PECL outputs. A simplified circuit schematic
of the PECL output cell is shown in Figure 5. All PECL
outputs are powered from V
ed from any voltage between +3.0V to V
interfacing with either +3.3V or +5V systems. The nomi-
nal V
All PECL outputs on the MAX108 are open-emitter
types and must be terminated at the far end of each
transmission line with 50Ω to V
MAX108 PECL outputs and their functions.
The MAX108 features an internal demultiplexer that
provides for three different modes of operation (see the
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 1. PECL Output Functions
14
PECL OUTPUT SIGNALS
CC
______________________________________________________________________________________
A0+ to A7+, A0- to A7-
P0+ to P7+, P0- to P7-
DREADY+, DREADY-
RSTOUT+, RSTOUT-
O supply voltage is +3.3V.
OR+, OR-
Demultiplexer Operation
CC
CC
O, which may be operat-
O - 2V. Table 1 lists all
Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.
Overrange True and Complementary Outputs
Reset Output True and Complementary Outputs
Digital Outputs
CC
D for flexible
following sections on Demultiplexed DIV2 Mode, Non-
Demultiplexed DIV1 Mode, and Decimation DIV4
Mode ) controlled by two TTL/CMOS-compatible inputs:
DEMUXEN and DIVSELECT.
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSE-
LECT low selects demultiplexed DIV2 mode, and DIV-
SELECT high selects decimation DIV4 mode (Table 2).
Figure 5. Simplified PECL Output Structure
FUNCTIONAL DESCRIPTION
500
GNDD
DIFF.
PAIR
1.8mA
500
GNDD
GNDD
V
A_+/P_+
A_-/P_-
CC
O