XR16L580 Exar Corporation, XR16L580 Datasheet - Page 24

• Manufacturer Part Number: XR16L580
• Description: Smallest 2.25 to 5.5V Uart With 16-Byte Fifo And Power-save
• Manufacturer: Exar Corporation

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
4.5
4.5.1
4.5.2
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details.
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from
low to high.
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from low to
high.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by EFR
bit-7.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by EFR
bit-6.
Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s) that
generated the interrupt(s) is (are) read from the FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading the RHR register.
TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
MSR interrupt is cleared by reading the MSR register.
Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
Special character interrupt is cleared by reading the ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by reading the MSR register.
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
Table
7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
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REV. 1.2.0