XR16L784 Exar Corporation, XR16L784 Datasheet - Page 21

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

The receiver section contains an 8-bit Receive Shift
Register (RSR) and a byte-wide Receive Holding
Register (RHR). The RSR uses the 16X or 8X clock
for timing. It verifies and validates every bit on the in-
coming character in the middle of each data bit. On
the falling edge of a start or false start bit, an internal
receiver counter starts counting at the 16X (or 8X)
clock rate. After 8 (or 4) clocks the start bit period
should be at the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is validat-
ed. Evaluating the start bit in this manner prevents
the receiver from assembling a false character. The
rest of the data bits and stop bits are sampled and
validated in this same manner to prevent false fram-
ing. If there were any error(s), they are reported in the
LSR register bits 1- 4. Upon unloading the receive
data byte from RHR, the receive FIFO pointer is
bumped and the error flags are immediately updated
to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt up-
on receiving a character or delay until it reaches the
FIFO trigger level. Furthemore, data delivery to the
host is guaranteed by a receive data ready time-out
function when receive data does not reach the re-
ceive FIFO trigger level. This time-out delay is 4 word
lengths as defined by LCR[1,0] plus 12 bits time. The
RHR interrupt is enabled by IER bit-0.
F
4.7 R
IGURE
(8X M O D E R e gister)
(X off1/2 a nd X on 1/2 R e g.
A uto S oftw a re F lo w C on tro l
A uto C T S F low C o n trol (C T S # p in)
F lo w C o ntrol C ha ra cte rs
ECEIVER
12. T
1 6X or 8X C lock
RANSMIITTER
D ata B yte
T ran sm it
O
PERATION IN
FIFO
T ran sm it D a ta S hift R e g iste r
AND
F
(64 -B yte)
T ran sm it
LOW
F IF O
(T S R )
21
The receive holding register is a 8-bit register that
holds a receive data byte from the receive shift regis-
ter (RSR). It provides the receive data interface to the
host processor. The host reads the receive data byte
on this register whenever a data byte is trasferred
from the RSR. RHR is also part of the receive FIFO of
64 bytes by 11-bit wide, 3 extra bits are for the error
flags to be in LSR register. When the FIFO is enabled
by FCR bit-0, it acts as the first-out register of the
FIFO as new data are put over the first-in register. Ev-
ery time a read operation is made to the receive hold-
ing register, its FIFO data pointer is automatically
bumped to the next sequential data location. Also, the
error flags associated with the data byte are immedi-
ately updated onto the line status register (LSR) bits
1-4.
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter and
receiver. The rate is programmed through registers
DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See Programmable Baud Rate
Generator section for more detail.
DLM)
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
C
4.8 R
4.8.1 Receive Holding Register (RHR)
4.8.2 Baud Rate Generator Divisors (DLL and
ONTROL
EGISTERS
M
ODE
T H R In terru pt (IS R bit-1) fa lls
w he n b eco m es em pty. F IF O
b elo w P rog ra m m e d T rig ge r
is E n a ble d by F C R bit-0 = 1
L evel (T X T R G ) an d th en
T X F IF O 1
XR16L784
REV. 1.0.1