XR16L784 Exar Corporation, XR16L784 Datasheet - Page 24

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
• CTS#/DSR# is by a change of state on the input pin
• RTS#/DTR# is when its receiver changes the state
• LSR interrupt is cleared by a read of the LSR regis-
• RXRDY is cleared by reading data until FIFO falls
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR con-
tents may be used as a pointer to the appropriate in-
terrupt service routine.
Logic 1 = No interrupt pending. (default condition)
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a log-
ic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xon or Xoff character(s).
N
a logic 1 until a Xon character is received. ISR bit-5 indi-
cates that CTS#/DSR# or RTS#/DTR# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
P
4.11.2 Interrupt Clearing:
OTE
with auto flow control enabled by EFR bit-7, and
depending on selection on MCR bit-2.
of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
ter.
below the RX FIFO trigger level.
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
: Note that once set to a logic 1, the ISR bit-4 will stay
Table 9
B
IT
0
0
0
0
0
0
1
0
).
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
EGISTER
IT
T
0
0
1
0
0
0
0
0
ABLE
-3
9: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
24
B
• RXRDY Time-out is cleared by emptying the FIFO.
• TXRDY interrupt is cleared by a read of the ISR
• MSR interrupt is cleared by a read of the MSR reg-
• Xon, Xoff or Special character interrupt is cleared
• RTS#/DTR# output status change interrupts is
• CTS#/DSR# input status change interrupts is
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
FCR BIT-0: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO. (de-
fault).
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive FIFO reset. (default)
Logic 1 = Reset the receive FIFO pointers and FIFO
level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
IT
0
0
0
0
0
0
0
1
4.11.3 FIFO Control Register (FCR)
register.
ister.
by a read of the ISR.
cleared by a read of the ISR register.
cleared by a read of the MSR register.
-0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default)
P
RIORITY
L
S
EVEL
OURCE OF THE INTERRUPT
+