XR16L784 Exar Corporation, XR16L784 Datasheet - Page 32

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
DTR can take effect. The selection for RTS# or DTR#
is through MCR bit-2. RTS/DTR# pin will function as a
general purpose output when hardware flow control is
disabled.
• Logic 0 = Automatic RTS/DTR flow control is dis-
• Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
• Logic 0 = Automatic CTS/DSR flow control is dis-
• Logic 1 = Enable Automatic CTS/DSR flow control.
Transmit FIFO level byte count from 0x00 (zero) to
0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The
FIFO level Byte count register is read only. The user
can take advantage of the FIFO level byte counter for
faster data loading to the transmit FIFO., which re-
duces CPU bandwidth requirements.
An 8-bit value written to this register sets the TX FIFO
trigger level from 0x00 (zero) to 0x40 (64). The TX
FIFO trigger level generates an interrupt whenever
the data level in the transmit FIFO falls below this
preset trigger level.
Receive FIFO level byte count from 0x00 (zero) to
0x40 (64). It gives an indication of the number of
characters in the receive FIFO. The FIFO level byte
count register is read only. The user can take advan-
tage of the FIFO level byte counter for faster data un-
loading from the receiver FIFO, which reduces CPU
bandwidth requirements.
Counter, read-only
Level, write only.
Counter, read only
Level, write only
4.11.12 TFCNT[7:0] : Transmit FIFO Level
4.11.13 TXTRG [7:0]: Transmit FIFO Trigger
4.11.14 RFCNT[7:0]: Receive FIFO Level
4.11.15 RXTRG[7:0]: Receive FIFO Trigger
abled. (default)
abled. (default)
Transmission stops when CTS/DSR# pin de-
asserts to logic 1. Transmission resumes when
CTS/DRS# pin returns to a logic 0. The selection
for CTS# or DSR# is through MCR bit-2.
32
An 8-bit value written to this register, sets the RX
FIFO trigger level from 0x00 (zero) to 0x40 (64). The
RX FIFO trigger level generates an interrupt whenev-
er the receive FIFO level rises to this preset trigger
level.
I/O SIGNALS
DTR#[ch-3:0]
REGISTERS
RTS#[ch-3:0]
IRTX[ch-3:0]
TX[ch-3:0]
XCHAR
RFCNT
RFTRG
TFCNT
TFTRG
XOFF1
XOFF2
FCTR
XON1
XON2
MCR
MSR
DLM
RHR
THR
FCR
LCR
LSR
SPR
EFR
DLL
IER
ISR
T
ABLE
15: UART RESET CONDITIONS
Bits 7-4 = logic levels of the inputs
Bits 3-0 = logic 0
RESET STATE
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
RESET STATE
Logic 1
Logic 0
Logic 1
Logic 1