XR17D154 Exar Corporation, XR17D154 Datasheet - Page 23

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
The THR and RHR register address for channel 0 to channel 3 is shown in
for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit
data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR
register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
There are 4 UARTs [channels 3:0] in the D154. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
4.2
5.0 UART
D a ta B it-3 1
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
P C I B u s
R
EAD
B 7
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT.
B 6
R e ce ive D a ta B yte n + 1
RX FIFO,
Etc
B 5
E
T
ABLE
RRORS
B 4
C H 0 0x00 0 R ead R H R
C H 2 0x40 0 R ead R H R
C H 3 0x60 0 R ead R H R
C H 3 0x60 0 W rite T H R
C H 1 0x20 0 R ead R H R
C H 0 0x00 0 W rite T H R
C H 1 0x20 0 W rite T H R
C H 2 0x40 0 W rite T H R
B 3
8: T
B 2
THR and RHR Address Locations For CH0 to CH3 (16C550 Com patible)
RANSMIT AND
B 1
Channel 0 to 3 Receive Data with Line Status Register in a 32-bit alignm ent through
FIFO Data n+1
FIFO Data n+3
B 0
the Configuration Register Address 0x0180, 0x0380, 0x0580 and 0x0780
B
B 7
YTE
L in e S ta tu s R e g iste r n + 1
B 6
3
R
B 5
ECEIVE
B 4
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B 3
D
ATA
B 2
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B 1
R
LSR n+1
LSR n+3
B
EGISTER IN
B 0
YTE
23
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B 7
2
B 6
R e ce ive D a ta B yte n + 0
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B 5
B
YTE FORMAT
B 4
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B 3
FIFO Data n+0
FIFO Data n+2
B 2
B
B 1
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
YTE
Table 8
, 16C550
B 0
1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B 7
below. The THR and RHR
78 4T H R R H R 1
L in e S ta tu s R e g iste r n + 0
B 6
COMPATIBLE
PRELIMINARY
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B 5
B 4
áç
áç
áç
áç
B 3
LSR n+0
LSR n+2
B
YTE
B 2
B 1
0
D a ta B it-0
P C I B u s
B 0