XR17D154 Exar Corporation, XR17D154 Datasheet - Page 35

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
IER[3]: Modem Status Interrupt Enable
IER[4]:
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
INTERRUPT STATUS REGISTER (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table,
associated with each of these interrupt levels.
I
I
NTERRUPT
NTERRUPT
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
Logic 0 = Disable the RTS# interrupt. (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# output pin makes a
transition.
Logic 0 = Disable the CTS# interrupt. (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# input pin makes a transition.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by the a 4-char plus 12 bits delay timer if data doesn’t reach FIFO trigger level.
TXRDY is by LSR bit-5 in the non-FIFO mode, TX trigger level setting in the FIFO mode (or bit-6 in auto
RS485 control).
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS#/DSR# is by a change of state on the input pin with auto flow control enabled, EFR bit-7, and depending
on selection on MCR bit-2.
RTS#/DTR# is when its receiver changes the state of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by emptying the RX FIFO.
TXRDY interrupt is cleared by a read to the ISR register.
MSR interrupt is cleared by a read to the MSR register.
Xon, Xoff or Special character interrupt is cleared by a read to ISR register.
RTS#/DTR# output status change interrupt is cleared by a read to the ISR register.
CTS#/DSR# input status change interrupt is cleared by a read to the MSR register.
Table
Reserved.
G
C
12, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
LEARING
ENERATION
:
:
35
PRELIMINARY
áç
áç
áç
áç